ASDeX-driven Analog Circuit Verification - FAC 2013fac2013.imag.fr/FINAL/MaSlides.pdfWorkshop...

Workshop Frontiers in Analog CAD, Berkeley, Feb. 14th-15th 2013

ASDeX-driven Analog Circuit Verification

Mingyu Ma, Lars Hedrich Department of Computer Science Goethe University Frankfurt am Main, Germany

Sebastian Steinhorst TUM CREATE Singapore

Mingyu Ma Goethe University Frankfurt

FAC 2013 Feb. 14th – 15th 2013 Berkeley, CA, USA

Outline

Introduction

ASDeX and AXEI

ASDeX-driven Work-Flow

Conclusion

Introduction

Motivation: - Specification for analog circuits mostly written in text

Complex description misunderstanding - Verification methodologies

Difficult to understand without additional documentation Rarely implemented by end users

- IP-XACT for digital circuits [IEEE SA-1685-2009] - ASDeX integrated successfully into validation and synthesis workflow

Aim: - Integration of ASDeX-format into analog verification workflow

Include all relevant information - An interface from ASDeX to target tools

ASL & assertion based model checking [1] Other verification methodologies

Introduction

Assertion-based Verification

Introduction

ASDeX-driven Design Flows

Introduction

DUV´s specification in ASDeX

specification testbench function task

AXEI & Templates

ASDeX-driven Design Flows

Introduction

DUV´s specification in ASDeX

specification testbench function task

AXEI & Templates

Concept for Code Generation using AXEI

Template

Input: - ASDeX file set - Code templates

ASDeX and AXEI

ASDeX Engine Interface: - Python - Parser - Generator

Template

AXEI Generator

ASDeX and AXEI

ASDeX Engine Interface: - Python - Parser - Generator

Template

AXEI Generator

Target Code

VHDL-AMS PERL

ASL ASDeX

……

Output: - Target code for design tools - New values of circuit’s properties in ASDeX - Documentation

ASDeX and AXEI

Overview of ASDeX Structure

Contents:

All relevant parameters of specification

Properties of analog circuits

Ports with characteristics

Operating parameters &

environmental conditions

Information about measurement, testbench and simulation

ASDeX: Analog Specification Description in XML

Formalization through XML-Schema-Definition (XSD)

ASDeX and AXEI

Overview of ASDeX Structure

Contents:

All relevant parameters of specification

Properties of analog circuits

Ports with characteristics

Operating parameters &

environmental conditions

Information about measurement, testbench and simulation

ASDeX: Analog Specification Description in XML

Formalization through XML-Schema-Definition (XSD)

ASDeX and AXEI

Mapping Sub-Blocks in the Task Block

ASDeX and AXEI

log XZ pY

log UZ pU

ASDeX and AXEI

log XZ pY

log UZ pU

ASDeX and AXEI

log XZ pY

log UZ pU

ASDeX and AXEI

ASDeX Specification

ASDeX TB-Library

TB component connects to

port A and

port B

Definition: Port input Port output

A = input B = output

Template

Examples: Generation of Testbench Code

ASDeX AXEI

Generator

Target Code VHDL-

AMS PERL

ASL ASDeX

……

ASDex-driven work-flow

Template

ASDeX AXEI

Generator

Target Code VHDL-

AMS PERL

ASL ASDeX

……

<Specification> <ports> <port><name>in1</> <port><name>output</>

<Task-tb_port_mapping> <tb_port_mapping> <port_name>output</> <te_net_name>Uout</> <tb_port_mapping> <port_name>in1</> <tb_net_name>inp</>

Template

Template (Mako)

ASDeX AXEI

Generator

<Specification> <ports> <port><name>in1</> <port><name>output</>

<Task-tb_port_mapping> <tb_port_mapping> <port_name>output</> <te_net_name>Uout</> <tb_port_mapping> <port_name>in1</> <tb_net_name>inp</>

Mapping: % for spec_port in ports.port: % if spec_port.get_name( ) == mapp.port_name: % spec_port.set_name(mapp.tb_port_name)

spv (instanz(ref_name, `Uin´), netinp, 0, p1=1.5);

SPICE like netlist file

Generation: % ${cp.nature} (instanz(ref_name, `${cp.name}´), net${dc_supply.p_net}, ${dc_supply.n_net}, ${cp_par.name}=${cp_par.value});

FAC 2013 Feb. 14th – 15th 2013 Berkeley, CA, USA 19

Examples: Generation of Function Code

Template

AXEI Generator

Target Code VHDL-

AMS PERL

ASL ASDeX

……

Template

AXEI Generator

Target Code VHDL-

AMS PERL

ASL ASDeX

……

ASDeX <Function><name>slew-rate</> <object_name>IN</> <object_name>OUT</> <variable_name>low</> <variable_default><value>0.2</> <divide/> <apply><minus/> <apply><fn><ci>max</></> <ci>OUT</></> <apply><fn><ci>min</></> <ci>OUT</></></> <apply><fn><ci>risetime</></> ……

<Ref_function><ref_name>slew-rate</> <func_mapping> <object_in_function>IN</> <tb_net>inp</> <func_mapping> <object_in_function>OUT</> <tb_component>output</> <parameter_override> <variable_name>low</> <value>0.1</>

Template

AXEI Generator

ASDeX <Function><name>slew-rate</> <object_name>IN</> <object_name>OUT</> <variable_name>low</> <variable_default><value>0.2</> <divide/> <apply><minus/> <apply><fn><ci>max</></> <ci>OUT</></> <apply><fn><ci>min</></> <ci>OUT</></></> <apply><fn><ci>risetime</></> ……

<Ref_function><ref_name>slew-rate</> <func_mapping> <object_in_function>IN</> <tb_net>inp</> <func_mapping> <object_in_function>OUT</> <tb_component>output</> <parameter_override> <variable_name>low</> <value>0.1</>

Template (Mako) % for child in function.iter(): %% %% Build the equation %% Replace the object name %% Override the variable value %% Transform to the target code function %%

ΔOUT / risetime

Function ASL(macro) file

numvar %intern_output_min, …… ; on steady assign(%intern_output_min,min) value(OUT)[-inf,inf]; on steady assign(%intern_output_max,max) value(OUT)[-inf,inf]; ……

ASDeX Verification Run

GUI Automatic Automatic Automatic Automatic Automatic Automatic

Specification description in ASDeX Format Testbench & Function Generation Properties Assertion Simulation Model Checking Evaluation Documentation Generation

180nm Technology

GUI Automatic Automatic Automatic Automatic Automatic Automatic

Conclusion

An ASDeX-driven verification framework

All necessary methods provided by AXEI

Case study

An higher degree of automation and formalization in verification process

Better usability for end users

Workshop Frontiers in Analog CAD, Berkeley, Feb. 14th-15th 2013

Thank you for your attention!

ASDeX Home Page: www.em.cs.uni-frankfurt.de/asdex

Signal Transition (1)

Signal Transition (2)

Description in Function Block

ASDeX and AXEI

Formulas described in MathML format

Name of the function

List of the objects to be calculated

List of the variables, which are defined in the function

Variable´s name

Default value of the variable

Path for a pre-defined function description in mathML

mathML description block

Needed for property parameters calculation, e.g. in a function library of the model checking work flow [1].

Description in Function Block

Formulas described in MathML format

ASDeX and AXEI

log XZ pY

Objects Variable

Needed for property parameters calculation, e.g. in a function library of the model checking work flow [1].

Examples: Generation of Ocean Scripts

Template

AXEI Generator

ASDeX <Function> <object_name>X</> <object_name>Y</> <variable_name>low</> <variable_default><value>0.1</> <mrow> <mi>psrr</> <mo>=</> <mn>20</> <mi>log</> <mo>(</> <mrow> <mi>X</> <mo>(</> <mi>freq</> <mo>)</> </> <mo>/</> <mrow> <mi>Y</> <mo>(</> <mi>freq</> <mo>)</> </> <mo>)</> </>

<Ref_function> <func_mapping> <object_in_function>X</> <tb_component>Vcc</> <func_mapping> <object_in_function>Y</> <tb_component>Vos</> <parameter_override> <variable_name>freq</> <value>10</>

{(dB20(value(mag(getData("/Vcc" ?result "xf-xf")) 10)) - dB20(value(mag(getData("/Vos" ?result "xf-xf")) 10)))}

Template (Mako) % for child in function.iter(): %% %% Build the equation %% Replace the object name %% Override the variable value %% Transform to the target code function %%

Topology Synthesis from ASDeX

PSRR = 20log(Vcc(freq=10)/Vos(freq=10))

Ocean Script

Comparison

Conclusion

Manual design flaw avoided Time saved, through the fully automatic framework

Comparison

Conclusion

asdex::specIO::class docs doc_output asdex_output

Comparison

Conclusion

Comparison

Conclusion

asdex::specIO::class docs doc_output asdex_output

Comparison

Conclusion

Comparison

Conclusion

ASDeX-driven Analog Circuit Verification - FAC 2013fac2013.imag.fr/FINAL/MaSlides.pdfWorkshop...

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