Accelerating Analog Verification Visually-assisted Automation … · • Accelerating Analog Verification • Visually-assisted Automation for Custom Design Improving Analog and Mixed

Damian Roberts & Francois Thomas

April 29th, 2016

• Accelerating Analog Verification

• Visually-assisted Automation for Custom Design

Improving Analog and Mixed Signal Productivity

Damian Roberts

April 29th 2016

Accelerating Analog Verification

Specification Driven AMS Verification Environment

© 2016 Synopsys, Inc. 3

Growing Analog Verification Complexity

Addressing the growing complexity

• Faster simulation

– New algorithms in SPICE and FastSPICE

• Modern analysis environment

– Managing massive simulations & data explosion

PVT corners

Multi-Testbenches

Monte Carlo simulation

Mixed-Signal

Reliability


Custom Compiler - SAE

• Simulation Setup

– Common environment across simulation portfolio

– Multiple Testbench Environment

– Parametric, corners, Monte Carlo

– Specification capture

– Parasitic simulation (estimated and post layout)

• Comprehensive simulation management utilities

– Save and reuse simulation setup

– Batch scripting

– Distributed processing

• Analysis and debug

– Advanced data mining and charting

– Results post processing and data mining

– HTML report generation

Specification Driven Simulation Analysis Environment

Simulation

Management

Analysis &

Debug

Testbench Setup

OA Schematic or Netlist (SPICE, SPF, DSPF, Verilog)

CustomSim (FastSPICE)

FineSim SPICE (Accelerated SPICE)

HSPICE (SPICE)

VCS AMS

CustomSim VCS

Precision

Performance

Giga Scale


Expression, measurements

and goals

Analysis setup Design parameters

Streamlined Simulation Setup Single Testbench (STB) Environment

Simulation

Management

Analysis &

Debug

Testbench Setup

Design Data

Results analyser

View & crossprobe in

WaveView Simple use model, progressing to MTB


Streamlined Simulation Setup MultiTestbench (MTB) Environment

Simulation

Management

Analysis &

Debug

Testbench Setup

Results from one testbench

‘chained’ to another

Local or global

design parameters

Same design but with

multiple testbeches

Simulate and analyse the same design

across multiple testbenches

Design Data


Streamlined Simulation Setup Specification Capture

Simulation

Management

Analysis &

Debug

Testbench Setup

Expression, measurements Enables automatic checking of

specifications in Results Viewer

Design Data


Streamlined Simulation Setup Schematic and text view integration

Simulation

Management

Analysis &

Debug

Testbench Setup

Language-sensitive text editor streamlines

netlist based verification

Language support:

Verilog, VerilogA, VerilogAMS,

SystemVerilog and SPICE Hierarchy Traversal

from text to schematic

Back-annotation

of node voltages

Outputs probing from

text

Design Data


Simulation Management Advanced analysis setup

Simulation

Management

Analysis &

Debug

Testbench Setup

Comprehensive Sweeps, Corners and Monte

Carlo simulation

Easy corners definition and selection

for further design exploration/tuning Design Data


Simulation Management Common environment across simulation portfolio

Simulation

Management

Analysis &

Debug

Testbench Setup

Netlist (SPICE, SPF, DSPF, Verilog

Multi-testbench with history support

Job monitoring of local and remote runs

Multiple Testbench support

History fully available for all

testbenches

Hierarchical Job Monitor

tracks all runs progress


Analysis and Debug Results Viewer

Simulation

Management

Analysis &

Debug

Testbench Setup

Dynamic data filter and result comparison

Tight integration to Custom WaveView Back-annotation of

Operating Points

Results visible as they

become available

Visual indicators for pass,

fail or within margin

Dynamic filtering

Passed/failed/All

Results comparison tool for easy

comparisons across history points

Design Data


Analysis and Debug Data mining

Simulation

Management

Analysis &

Debug

Testbench Setup

Comprehensive data mining with advanced

statistical and multi-parameter charting Back-annotation of

Operating Points

Statistical charts

Multi-parameter charts

Design Data


Analysis and Debug HTML Reports

Simulation

Management

Analysis &

Debug

Testbench Setup

Web-based report generation and sharing Back-annotation of

Operating Points

Full report with hyperlinked table

of contents for quick access

Report also includes saved

waveform images

Detailed Measurement

section

Design Data

Videos/SAE_ReportGen_V2.mp4

Francois Thomas

April 29th, 2016

Speed of automation with the control and creativity of manual layout

Visually-assisted Automation for Custom Design


Text Based Constraint-driven

Automation

Layout

Edit Textual

Constraints

Circuit

Design

Edit Textual

Constraints

…

The long awaited solution for layout speed up

without the trap of « digital like » automation:

Low adoption by analog designer:

perceived lost of control/creativity

Visually-assisted

Circuit

Design

Visually-

assisted

Layout

Fast adoption by analog designer:

speed and designer creativity


Visually Assisted Layout


Layout Assistants

Visually-Assisted Automation

Co-Design

Assistants

Layout

Assistants

In-Design Assistants

Template

Assistants

• User-guided device placement and routing /

symbolic device manipulation

• Fast connections for FinFET

and high M factor devices

• Auto generates constraints for templates from

schematic smart analisys

Key benefits

• Get layout finished faster

• User stays in full control for hand-crafted results Speed up layout tasks

Videos/SNUG_Video1.mp4



• DRC during layout

• Catch electro-migration and IR drop errors

• Visualize R & C during layout

• Built-in StarRC engine

Key benefits

• Reduce DRC signoff iterations

• Reduce post-layout simulation surprises

Reduce iterations



Template Assistants

Visually-Assisted Automation

Co-Design

Assistants

Layout

Assistants


Template

Assistants

• Built-in template library for common circuits

• Template finder matches circuits in schematic

with templates

• Create and use new templates

Key benefits

• Complete layout much faster

• Leverage knowledge of experienced designers

Reuse know-how of best designers!



Putting it All Together Synopsys experience of visually assisted methodology

Symbolic Editor

for device

placement

Synopsys MSIP: Standard Cell Layout on 10nm

Templates for

pre-defined

architectures

Track and via

planner for

routing

DRC

correct final

layout


Visually Assisted V.S. Conventional Layout Methodology

• This video shows comparison of a 10nm Multiplexer cell layout using Visually Assisted vs.

conventional layout methodology.

• Speed up is maximum in advanced technologies: more complex rules, grid based design,

coloring (multi patterning), …

• A lot of features develop for FinFet process add a lot of productivity to other apllication: for

example features such as cloning developed for high M factor Xtor in FF boost productivity of

SmartPower design also us large M factors.

• The videos are speed up to compare the two methods

• Notice the large amount of zooming in/out in the conventional methodology


Visually Assisted V.S. Conventional Layout Methodology

Conventional Layout Methodology No assistants

Placement is FIN based

Minimal use of tracks

Layout style identical to planar

Visually assisted layout Layout assistants

Placement is track based

Heavy use of grids

Shapes colored by Nets

New Layout Methodology

1 hr

8 min

Methodology implemented in Custom Compiler

Documents

Accelerating Analog Verification Visually-assisted Automation … · • Accelerating Analog Verification • Visually-assisted Automation for Custom Design Improving Analog and Mixed