An Approach to Model Based Code Generation for a ... fileAn Approach to Model Based Code Generation...

An Approach to Model Based Code Generationfor a Specialized Soft Microprocessor

Elena Rozova1, Bernd Däne2

1Software Architectures and Product Lines Group2Computer Architecture and Embedded Systems Group

Technische Universität Ilmenau, Germany

AutSys-2015

• Introduction

• Concept of case study

• Overview of the soft microprocessor

• Design flow and detail solutions

• Results

• Conclusion and further work

Topics

Supported by Deutsche Forschungsgemeinschaft (DFG)and by Thüringer Aufbaubank (TAB and EFRE).

Introduction

Use of FPGAs (Field Programmable Gate Arrays)in Embedded Systems:

Advantages in performance and flexibility

Algorithms can be implemented directly or with soft microprocessors

Use of FPGAs (Field Programmable Gate Arrays)in Embedded Systems:

Advantages in performance and flexibility

Algorithms can be implemented directly or with

Challenge: Design processes

Concept of Case Study

Embedding project: Soft microprocessor LiSARD1

Real-time signal processing (controllers, filters)

Double precision floating point operation

Case study investigates graphical design processusing the LabVIEW tool

Goal: Model based code generation and optimization

1 LabVIEW integrated Softcore Architecture for Reconfigurable Devices

Overview of the Soft Microprocessor

Application specific processor architecture Configurable instruction set Omitting unneeded features

Simple pipeline: No dependency logic

Multi-core, shared memory

Pipeline Architecture

ProgramMemory

ReadInterface

ProgramMemory

ReadInterface

InstructionFetch

InstructionDecode

OperandFetch Execute Write Back

InstructionDecoder

DataMemory

ReadInterface

DataMemory

ReadInterface

Source2Source1

ExecuteModeWriteBackOperationTarget

ALUALU

DataMemory

WriteInterface

DataMemory

WriteInterface

InputRegisters

OutputRegistersOutput

Registers

Code Generation and Optimization

Fully pipelined operators Exploit micro parallelism by instruction scheduling

Static approach Full timing defined at compile time

Optimization strategies crucial for performance

Explained with simple example program

Example Program

in 1 ? x1in 2 ? x2in 3 ? x3in 4 ? x4mul x1 k1 t1mul x2 k2 t2add x1 x2 t3sub x3 x4 t4

11116655

Total, not optimized:

26 clock cycles

Source 1 Source 2

Pre-oper. 1 Pre-oper. 2 Instruction Destinat.

Program memory

00 01 02 03 04 05 06 07 08 09 0A 0B

Data memory

Example Pipeline Optimization

00 01 02 03 04 05 06 07 08 09 0A 0B

IN1 - - -

Source 1 Source 2

Pre-oper. 1 Pre-oper. 2 InstructionDestinat.

Program memory Data memory

in 1 ? x1 1 clock cycle

IN1 - - -

00 01 02 03 04 05 06 07 08 09 0A 0B

IN2 - - -

Source 1 Source 2

IN1 - - -

IN2 - - -

00 01 02 03 04 05 06 07 08 09 0A 0B

00 08 - -

MUL 04

Source 1 Source 2

mul x1 k1 t1 6 clock cycles

IN1 - - -

IN2 - - -

00 08 - -

MUL 04

00 01 02 03 04 05 06 07 08 09 0A 0B

01 09 - -

MUL 05

Source 1 Source 2

mul x2 k2 t2 6 clock cycles

IN1 - - -

IN2 - - -

00 08 - -

01 09 - -

MUL 04

MUL 05

00 01 02 03 04 05 06 07 08 09 0A 0B

IN3 - - -

Source 1 Source 2

IN1 - - -

IN2 - - -

00 08 - -

01 09 - -

IN3 - - -

MUL 04

MUL 05

00 01 02 03 04 05 06 07 08 09 0A 0B

IN4 - - -

IN 03 t1

Source 1 Source 2

IN1 - - -

IN2 - - -

00 08 - -

01 09 - -

IN3 - - -

IN4 - - -

00 01 - -

MUL 04

MUL 05

ADD 06

MUL ADD

00 01 02 03 04 05 06 07 08 09 0A 0B

Source 1 Source 2

add x1 x2 t3 5 clock cycles

IN1 - - -

IN2 - - -

00 08 - -

01 09 - -

IN3 - - -

IN4 - - -

00 01 - -

02 03 -

MUL 04

MUL 05

ADD 06

MUL ADD

00 01 02 03 04 05 06 07 08 09 0A 0B

t1 04 ADD

NEG x4

Source 1 Source 2

sub x3 x4 t4 5 clock cycles

IN1 - - -

IN2 - - -

00 08 - - - -

01 09 - - - -

IN3 - - -

IN4 - - -

00 01 - - - -

02 03 -

NEG MUL 04

- - - -

MUL 05

- - - - - -

- - - -

ADD 06

- - - -

ADD 07

MUL ADD

00 01 02 03 04 05 06 07 08 09 0A 0B

Source 1 Source 2

Total: 12 clock cycles → Speedup: 2,1

Multi-Core Configurations

Multi-core setups: Multiple copies of memory No communication overhead

For n-core configuration:o 2 · n identical copieso 2 · n² individually addressable blocks

Tested so far:o Quad-core, logical memory space: 4,096 cellso Physical memory consumption: 262,144 bytes

Dual-Core Setup

Core 1

Core 2

Memory 1a

Memory 1b

Memory 2a

Memory 2b

Memory 3a

Memory 3b

Memory 4a

Memory 4b

Multi-Core Optimization

Schedule instructions to cores

Schedule variables to memory locations

Calculate dependencies and lifetimes

Duplicate variables if needed

General Design Flow

Operator Library

Processor Design

Code Design

Code Converter

Configuration

ofcores

Allocatevariables

Detectionof

dependencies

Searchfree

code line

Insertcode line

Check dependencies

Testbench

Configured

ProcessorMemory Init

DataProgram

Model based (currently)

Detail Solutions

Give some impression about graphical approach

Small model parts selected Total size:

o ~30 LabVIEW worksheets (Code Converter)o >100 LabVIEW worksheets (full project)

Code Converter Details

Experimental Results

Program Instruct. count Comment

FIR-64 196 Finite Impulse Response filter (64 coeff.)

Kalman-2 350 4x4 Kalman filter, calculated twice

6-Axes 866 Adaptive control algorithm, six channels

Ellipse 364 Ellipse regression for incremental sensors

Ellipse-4 1456 Same as above, four channels

0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized pipeline-optimized

Speedup by Pipeline Optimization

0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized 1-core 2-core 4-core

0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized

Speedup by Multicore Optimization

Conclusion

Graphical approach to classical compiler functions

Efficiency demonstrated

Advantages and weaknesses identified

Contributes to model based design processes

Goals for further research outlined

Further Work

Generating source code from models

Model based instruction set synthesis

Combined HW/SW optimization

Integrated configuration management

Thank you

your kind attention

An Approach to Model Based Code Generation for a ... fileAn Approach to Model Based Code Generation...

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