A Multi-Output On-Chip Switched-Capacitor DC-DC Converter...

A Multi-Output On-Chip Switched-Capacitor DC-DC Converter for Near- and Subthreshold

Power Modes

Yingbo Zhao1, Yintang Yang1

1Xidian University, Xi’an 710071, China

Kaushik Mazumdar2, Xinfei Guo2, Mircea R. Stan2

2University of Virginia, Charlottesville, VA 22904, USA

DC-DC Conversion

• Address power consumption concerns

-Various power-aware spatial and temporal scheduling schemes

• Achieve significant power savings

-Power supplies having multiple voltages allow circuits to operate in several

distinct power modes

Why Switched-Capacitor (SC) DC-DC Converter?

• Linear low-dropout regulators

-On-chip; Low efficiency for high step-down conversion

• Switching converters

Inductor-based converters

-High power performance; Off-chip

SC converters

-On-chip, high efficiency; Conversion ratio set by topology, unavoidable ripples

Motivation of Our Work

-Being fully on (or super-threshold)

-Low power (near-threshold)

-Ultralow power (subthreshold)

Load current variation with supply voltage for a

resistive load and a CMOS load

For circuits that operate in several

distinct power modes achieving

power savings, with the most

common modes

Motivation of Our Work

Energy per operation and energy savings

factor as a function of supply voltage for a

CMOS load

Circuits operate in several distinct power modes achieving energy saving

Use supply voltage as a powerful knob to

achieve energy saving

Structure of Proposed Multi-Output Converter

A

B

C

D

E

F

G

.

.

.

.2

3

4

5

6

Cfly2

Cfly1

.

.

.

VDD

C3

C4

C5

1

Vo2=2VDD/3

Vo1=VDD/3

Voltage Region 3

Voltage Region 2

Voltage Region 1

A (VDD)

B

D (GND)

E

F

G

.

.

.

.

Cfly2

Cfly1

.

.

.

Ф1

Vo2=2VDD/3

Vo1=VDD/3 G

F

E.

.

.

Cfly1

Cfly2

.

.

.

.

C

Ф2

Ф1

Ф2

Ф1

Ф2

Ф2

Ф1

Ф2

Ф1

Ф2

Ф1

cell 1 cell 2

Non-interleaved 2-way interleaved

Structure of Proposed Multi-Output Converter

A

D

E

F

G

.

.

..

.

.VDD

Cfly2

Cfly1

.

F

G.

.

F.Vo2=2VDD/3

Vo1=VDD/3

LO

AD

.

LO

AD I2

I1

Cfly2

Cfly1

Phase 1: Phase 2:

A

D

E

F

G

.

.

. .

.

.VDD

.

F

G .

.

F .

Cfly2

Cfly1

Cfly2

Cfly1

.

.

Vo2=2VDD/3

Vo1=VDD/3

LO

AD

.

LO

AD I2

I1

A (VDD)

B

D (GND)

E

F

G

.

.

.

.

Cfly2

Cfly1

.

.

.

Ф1

Vo2=2VDD/3

Vo1=VDD/3 G

F

E.

.

.

Cfly1

Cfly2

.

.

.

.

C

Ф2

Ф1

Ф2

Ф1

Ф2

Ф2

Ф1

Ф2

Ф1

Ф2

Ф1

cell 1 cell 2

Structure of Proposed Multi-Output Converter

VDD

2VDD/3

VDD/3

0

Ф1 Ф2

T

VE

VF

VG

Voltage Region 3

Voltage Region 2

Voltage Region 1

Vo2

Vo1

Voltage at node E, F and G transitioning

from Ф1 to Ф2 in three voltage regions

A (VDD)

B

D (GND)

E

F

G

.

.

.

.

Cfly2

Cfly1

.

.

.

Ф1

Vo2=2VDD/3

Vo1=VDD/3 G

F

E.

.

.

Cfly1

Cfly2

.

.

.

.

C

Ф2

Ф1

Ф2

Ф1

Ф2

Ф2

Ф1

Ф2

Ф1

Ф2

Ф1

cell 1 cell 2

Structure of Proposed Multi-Output Converter

Interleaving scheme

cell 1

.

.

.

.

.

.

A

D

B

C

cell 2

.

.

.

.

.

.

A

D

B

C

cell N

.

.

.

.

.

.

A

D

B

C

……

……

……

……

VDD

GND

Vo2=2VDD/3

Vo1=VDD/3

Architecture of the proposed converter in

multiphase interleaving mode

Voltage ripples

-The inherent loss arising from the flying capacitors charging/discharging process

Structure of Proposed Multi-Output Converter

……1 2 3 N/24 5 N-interleaved

8-interleaved

Non/2-interleaved

0.5T 0.5T

……1 2 3 N/24 5

Charge is divided into equal amount

flowing through each of the N units more

finely.

More importantly the impulsive charge

overlaps during each of the N-interleaved

clock phases, as a result reducing the

ripple significantly by the number of N

Unequally Sized Flying Capacitors

Iload∝αVDD2

I1＜ I2 Cfly1＜ Cfly2

We propose an optimization method that uses unequal flying capacitors to further

reduce the area of the SC converter

Conventionally, flying capacitors are sized equally for an SC converter

Unequally Sized Flying Capacitors

Cfly1＜ Cfly2

Flying capacitors play a crucial role in determining the amount of charge

which can be shuttled to the output port every clock cycle

How the output voltages will be affected?

When the two flying capacitors Cfly1 and Cfly2 are sized unequally, the

proposed multi-output SC converter is expected to transfer different

amount of charge to its two output ports

Unequally Sized Flying Capacitors

2 1

1

fly fly

fly

C CC

C

min

min

no al out

x

out no al

V VVV

V V

Output voltage constrain VX

Mismatch of the two flying capacitors

V

Voltage Drop

Vnominal

Vout

Output voltage constrain Vx as a function of ∆C

Simulation Results

To verify the validity of the multi-output topology and the method of using

unequal flying capacitors, a 4-way interleaved converter is implemented and

simulated in 45 nm CMOS technology

Techonolgy Max.

Freq.

Vin Max.

Iload

Total

Cfly

Cout Max.

Ripple

Area Peak

Eff.

45 nm CMOS

Single-output

40 MHz1 V 5 mA 3.7 nF

Single-output

0.5 nF Off-chip

9.6 mV 0.37

mm2

90%

@

1.3

mW

Dual-output

80 MHz

Dual-output

1 nF Off-chip

Simulation Results

10.0E-07

Time [s]

5.0E-072.5E-07 7.5E-070

0.2

0.8

0

0.4

Ou

tpu

t V

olt

age

[V] 0.6

5.0E-072.5E-07 7.5E-07 10.0E-07

Time [s]

0

0.1

0.4

0

0.2

Outp

ut

Volt

age

[V] 0.3

Output voltage with the maximum load

current (a) with conversion ratio of 2/3, (b)

with the conversion ratio of 1/3, and (c)

dual output operating mode

(a) (b)

(c)

Simulation Results

Efficiency with changes in load current (a) with conversion ratio of 2/3, and (b) with conversion ratio of 1/3

(a) (b)

Application for Different Power Modes

.

.

.

.

A

D

B

C

VDD

Vo2=2VDD/3

Vo1=VDD/3

BLOCK

1.

.

.

.

.

.

.

.

.SC

converter

load

BLOCK

2

BLOCK

3

• For circuits with discrete power modes

• For systems that use dithering to emulate a continuous range of voltage

such as the Panoptic Dynamic Voltage Scaling (PDVS)*

Application of the proposed SC converter with PDVS approach

*A. Shrivastava and B. H. Calhoun, A DC-DC converter efficiency model for system level analysis in ultra low power applications, J. Low Power Electron. Appl. 3 (2013).

Summary

• Provide multiple output voltages simultaneously

-Without changing the topology of the circuit

• Unequally sized flying capacitors-By taking advantage of the different levels of expected power consumption in the

various power modes

• SC converter achieves high efficiency over a wide range of load currents

THANK YOU!