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Research ArticleA High-Input Voltage Two-Phase Series-Capacitor DC-DCBuck Converter
Salahaldein Ahmed Rmila and Simon S Ang
Department of Electrical Engineering University of Arkansas Fayetteville AR 72701 USA
Correspondence should be addressed to Salahaldein Ahmed Rmila saa016uarkedu
Received 15 December 2019 Revised 19 April 2020 Accepted 23 April 2020 Published 8 June 2020
Academic Editor Herve Morel
Copyright copy 2020 Salahaldein Ahmed Rmila and Simon S Ang )is is an open access article distributed under the CreativeCommons Attribution License which permits unrestricted use distribution and reproduction in any medium provided theoriginal work is properly cited
A high-input voltage 2-phase series-capacitor (2-pscB) DC-DC buck converter is theoretically analyzed designed and imple-mented A new design approach for an automatic current sharing scheme was presented for a 2-phase series-capacitor syn-chronous buck converter)e series-capacitor voltage is used to achieve current sharing between phases without a current sensingcircuit or external control loop as each phase inductor charges and discharges the series capacitor to maintain its average capacitorvoltage constant A novel isolated gate driver circuit to accommodate an energy storage capacitor is proposed to deliver isolatedgate voltages to the switching transistors An I2 control scheme that uses only one feedback path control for the four gate drivers isproposed to enable higher voltage conversion An experimental 110-12V 6A load prototype converter was designed and itscurrent sharing characteristics were experimentally verified
1 Introduction
Two-phase series-capacitor buck converters were introducedto power laptops as low-voltage high-current voltage reg-ulator modules (VRMs) as well as nonisolated point-of-load(POL) converters [1ndash3] Automatic current sharing is im-portant to distribute heat generation in multiphaseswitching topologies at full load without the need to usecurrent sensing circuit or external control loop betweenphases Current sharing implementation for multiphaseswitching converter topologies is reported in [4ndash8] )eautomatic current sharing concept is the main feature of thisdouble step-down buck topology where the series capacitorwas utilized to accomplish current sharing 2-pscB is aunique converter topology that combines the benefits of aswitch capacitor circuit as a DC source and a two-phase buckconverter [9ndash11] Usually these converters are used as low-voltage (lt12V) POL voltage regulators [12]
In this work a high-voltage input (110V) 2-pscB con-verter is theoretically analyzed designed and implementedto examine the capability of current sharing at a highervoltage level and its impact on overall efficiency [13] A new
design methodology without using fudge factors or con-stants compared to previous designs [14] is used to im-plement an automatic current sharing scheme )e practicalimplementation of the 2-pscB converter is a challenging taskdue to the complexity of gate driver galvanic isolation due totiming mismatch between phase A switches )e two con-ventional bootstrap structures as shown in paper [1] areunsuitable for higher input voltages and bootstrap diodeisolation is not adequate to provide stability to gate driverreference voltage because voltage swing is common due tocharging and discharging of the series capacitor between thephase A gate drivers A new isolated gate driver circuit toaccommodate an energy storage capacitor is proposed todeliver isolated gate voltages to the switching transistors AnI2 control scheme that enables higher voltage conversion isproposed that uses only one feedback path control to drivethe 4 gate drivers An experimental 110-12V at 6A loadprototype converter was designed and its current sharingcharacteristics were experimentally verified to show that ahigher input voltage is possible compared to low inputvoltage [14 15] using an integrated circuit controller drivinginternal FETs of TPS54A20 Figure 1(a) shows the two-phase
HindawiJournal of Electrical and Computer EngineeringVolume 2020 Article ID 9464727 15 pageshttpsdoiorg10115520209464727
series-capacitor buck converter with automatic currentsharing
)e outline of the paper is as follows Section 2 describesthe fundamentals of this topology Section 3 derives themainparameters for the 2-pscB converter Section 4 describes theisolated gate driver circuit design Section 5 presents theproposed control scheme Section 6 presents the simulationresults using LTspice Section 7 shows the experimentalprototype and characterization results to illustrate thefunctionality and performance of the 2-pscB converterSections 8 and 9 provide discussion and the summary
2 Analysis of the 2-pscB Converter
A 2-pscB converter has four switching intervals the firstswitching interval D1T with Q11 and Q22 switching on thesecond and fourth switching intervalsD2Tand (1 minus d3)TwithQ12 and Q22 switching on and the third switching intervalD3T with Q12 and Q21 switching on Figure 1(b) shows thefour switching intervals and the switching devices that areswitched on during these intervals Hence
d2 minus d1( 1113857T D2T
d3 minus d2( 1113857T D3T
1 minus d3( 1113857T 1 minus D1 minus D2 minus D3( 1113857T
(1)
where T is the switching period At steady state during thefirst switching interval the high-side switch of phase Aswitch Q11 is switched on and the inductor current flowingthrough inductor L1 charges the series capacitor Cs [3 9])e duty cycle is given as
Vo
Vin
d1 d3 minus d2( 1113857
d1 + d3 minus d2
D1D3
D1 + D3 (2)
where d1 d2 and d3 represent switching intervals for theseries-capacitor buck modes When these intervals are thesame D1 D2 D3 D Hence
Vo
Vin
D
2 (3)
To achieve the current sharing balance between the twophases the switching voltage nodes must be the sameHence
Vcs
Vin
d1
d1 + d3 minus d2
D1
D1 + D3 (4)
From equations (2) and (4) at steady-state conditionsVo
Vcs D3 (5)
3 Derivation of Design Parameters
A new design approach for an automatic current sharingscheme is presented for the 2-pscB converter )e series-capacitor voltage is used to achieve current sharing be-tween phases without a current sensing circuit or externalcontrol loop as each phase inductor charges and dischargesthe series capacitor to maintain its average capacitorvoltage constant Design parameters are derived and ex-perimentally validated
)e main switches of both phases are driven at 180degphase shifts and with a duty ratio of less than 50 )einductor currents are defined as
IL1max min IR1plusmn
12
Vo
L11 minus D1( 1113857T1113890 1113891 IR1
plusmnΔiL1
2 (6)
IL2max min IR2plusmn
12
Vo
L21 minus D3( 1113857T1113890 1113891 IR2
plusmnΔiL2
2 (7)
where IL1max minand IL2max min
are the maximum andminimumvalues of phase A and B inductor currents IR1 and IR2 arethe average load currents at phase A and B respectively Inthis 2-pscB converter the total average output inductorcurrent is the sum of both the average phase inductorcurrents For a complete current sharing the peak-to-peakripple current of a single phase is
ΔiL1 ΔiL2
1L
Vin
2minus Vo1113874 1113875Ton1113876 1113877 (8)
vin
Q11
ndashiLCs
Cin
VCs
+
L2
Co
Q12
Q21
Q22
ioL1
RVo
+ndash
+
ndash
rCo
(a)
Q11 Q22
Q22
Q22
Q12
Q12 Q21
Q12
d1T
d2T
d3T
TTime (s)
Inte
rval
s
(b)
Figure 1 (a) Circuit schematic of the 2-pscB converter and (b) switching intervals
2 Journal of Electrical and Computer Engineering
where Ton D1T D3T As such a larger L and smaller Tonwill yield a smaller ripple current )e total average outputcurrent in terms of iL will be
Iout ILmax + ILmin
2 IR1
+ IR2 (9)
)e total inductor current at zero condition is equal tothe minimum value ILmin when Q11 is off in modes II andIV
ILmin iL(0) IL1min
+23IL2max
56Iout +
12
VoT
L
23
1 minus D3( 1113857 minus 1 minus D1( 11138571113876 1113877 (10)
When the load current contributed by each phase is atcomplete current sharing condition IR1
IR2 ( 12) Iout
the maximum inductor current value will be at full chargingof series capacitor in phase A and at fully discharging inphase B
ILmax iL d1T( 1113857 IL1max
+13IL2max
IR1+13IR2
+12
VoT
L
13
1 minus D3( 1113857 + 1 minus D1( 11138571113876 1113877
23Iout +
23
Vo
L( 1 minus D)T1113876 1113877
(11)
)us the peak-to-peak inductor current ripple is
ΔiL IL1maxminus IL1min
minus13IL2max
Vo
61
Lfsw5 minus 6D1 + D3( 1113857 minus
1R
1113888 1113889
56
Vo
L( 1 minus D)T1113876 1113877 minus
16Iout
16
5ΔiLphaseminus Iout1113876 1113877
(12)
where ΔiLphaseis phase A or B average current ripple at full
current sharing At continuous current mode (CCM) op-eration ILmin
is a positive value During current sharingwhen L1 L2 ILmin
gt 0 we have53IR1
minusVoT
L
1 minus d1( 1113857
2minus
d2 + 1 minus d3( 1113857
31113888 1113889gt 0 (13)
)e critical value for the two-phase inductors is then
Lcritical gtR
5fsw1 minus 3D1 + 2D3( 1113857 (14)
)e phase inductance should be within 15 to 2 timesthe critical inductance given in equation (14) to yield a goodefficiency Note that the efficiency of the converter in-creases with increasing inductance with performancedegradation in its transient response To avoid this effectthe inductance value should be chosen to provide
reasonable efficiency and good transient response As suchthe output inductor value can be expressed in terms of itscurrent ripple as
Lgt5R Vo (1 minus D)
fsw 6RΔiL + Vo1113858 1113859 (15)
)e instantaneous capacitor charge stored in one half ofthe switching period can be used to determine its outputcapacitance value as shown in Figure 2
ΔQ 12
T
41113874 1113875ΔiL2
CoΔVo (16a)
orΔVo
Vo
T
96Co
T
L5 minus 6D1 + D3( 1113857 minus
1R
1113874 1113875 (16b)
Hence during a complete current sharing
Co gt1
96fsw ΔVoVo( 1113857max
5Lfsw
(1 minus D) minus1R
1113888 1113889 (17)
Using the maximum and minimum output capacitorcurrent expressions
ΔiCo
1R + rCo
RΔiL minus Δvo( 1113857 (18)
For smaller output capacitor parasitic resistance rCoand
smaller Δvo ΔiCo ΔiL
Series-capacitor voltage VCs acts as an internal feedbackloop quantity to adjust the current sharing for the twophases As such if the inductor currents are not equal theseries-capacitor voltage would drift up or down and asmooth charging balance could not be maintained [16 17])is is because the average capacitor voltage remains con-stant only when the charge and discharging period balanceexists Inductor currents iL1 and iL2 charge and discharge theseries capacitor Cs respectively Figure 3 shows a simplifiedmathematical representation of 2-pscB converter with itsinternal current sharing mechanism resulting from the se-ries-capacitor voltage VCs including parasitic componentsIn steady-state conditions during automatic current sharingthe two inductor currents should be equal and then theaverage series capacitor voltage will be constant as well withapproximately half the input voltage across it and the seriescapacitor acts as a dc voltage source for the third intervalHence
Journal of Electrical and Computer Engineering 3
d1 Vin minus Vcs( 1113857 minus Vcs D3 0
Mode I langiCsrang langiL1rang
Mode II IV langiCsrang 0
Mode III langiCsrang minus langiL2rangwhere
langiCsrang langiL1rangD1 minus langiL2
rangD3 0
(19)
Using the iCs waveform shown in Figure 4 if IminD1 canbe neglected the minimum Cs value can be generalized andexpressed at complete current sharing as
ΔQ D1T IminD1 +12
D1TΔiL1
2 CsΔVCs (20)
Cs D1 Vo 1 minus D1( 1113857
4f2swL1 ΔVCs
+D1T IminD1
ΔVCs (21)
CsgtD2 ( 1 minus D)
4 L f2sw ΔVCsVCs( 1113857max
(22)
)e above equations enable design parameters such asCs Co and ∆iL to be determined
One of the technical advantages of multiphase is that thecombined output ripple (total ripple) is less than the ripplecurrent in each inductor (phase ripple) )is occurs due todriving the phases out of phase In case of the 2-pscBconverter at interleaving the phases with a proper timingcircuitry ripple current reductions can be easily achievedeven under unbalanced current sharing since the series-capacitor voltage can compensate for the current differencefor certain limits that results in much less output voltageripple Assuming all the ripple voltage is caused by thecapacitance of the output capacitor the approximated peakto the peak value of the total output current ripple to befiltered by the output capacitor is
ΔiL2pscB vo(1 minus 2D)
Lfsw
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)+
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)1113896 1113897 (23)
KRCM 2 1 minusm
NlowastD1113874 1113875(2m + 1 minus Nlowast2D) (24)
where KRCM is output current ripple cancellation multiplierN is the number of the phases and floor function returns thegreatest integer value less than the argument
m floor(NlowastD) (25)
where (m + 1)N geDgemN N gem ge 0Figure 5 shows that at certain duty cycle (D) value there
is a total cancellation of the ripple current according to theabove constraints For example total ripple current
cancellation for a 2-phase converter occurs beyond a dutycycle of 025 whereas for a 4-phase converter this totalripple current cancellation occurs at duty cycle beyond 0125and between a duty cycle of 025 and 0375 as shown inFigure 5
4 A Novel Isolated Gate Driver
Figure 6 shows the gate driver circuit using a UCC27531gate driver to accommodate adding a series capacitorbetween switches Q11 and Q12 of the phase A [18] where
iCo
(∆iL2) = (∆iCo2)
t
iComax
iComin
(12)d1T
D1T(32)d1T
Q
Figure 2 Instantaneous output capacitor circuit
+
+
+ndash
+
+
Control
++
+ndash
VoVin
IL1
IL2 IO
ICsVCs
D1
D3
Automatic current sharing
++
Figure 3 Self-balancing technique for 2-pscB converter
ΔvCsvin2
iCs
vCs
iminD3
imaxD3
imaxD1
T
ΔiL12
D1T D3T
ΔiL22t
t
Q
Q
Figure 4 Series-capacitor current and voltage at steady state
4 Journal of Electrical and Computer Engineering
the gate reference voltage for the isolated high-sideswitch is the positive side of Cs whereas the gate voltagefor the low-side switch circuit requires a different iso-lation loop since its reference voltage is ground As suchan isolation scheme must encompass the entire high-sideswitch circuit because inserting a series capacitor willintroduce a time delay between the gate voltages of thetwo switches
)is will interfere with the synchronization of theswitching time and voltage level Isolation scheme is re-quired to isolate the ground loops this means there shouldbe no direct conduction path between the high-side driverand the synchronous rectifier switch driver due to thevoltage storage element of Cs )e anode of bootstrap di-odes DBstrap1 is commonly connected to a driver sourceVDD)erefore bootstrap capacitors C5 to C8 are charged bya voltage difference between the driver source voltage VDDand the series-capacitor voltage VCs during the on-times ofthe Q12 switch through the bootstrap diode DBstrap1 Since
the four bootstraps diodes are isolated using an isolated DCsource the gate voltages of the main switches Q11 andQ21 areenough to charge the bootstrap capacitors As such phase Buses the same gate drivers as phase A To reduce the cost ofthe four matched bootstrap capacitors for each gate driverC5 to C8 two of them can be eliminated For voltage higherthan 12V external FETs are used for better heat distributionand isolation [15] )e gate driver should be located as closeto the MOSFETs as possible In this way self-inductance andself-resistance of the traces will be reduced to minimizevoltage spikes and reduce EMI For a complete currentsharing dead time must be the same for both phases In theproposed circuit there are two ways to adjust the dead timebetween the high-side signal and low-side signal using twovariable resistors before and after the optocoupler Currentsink loops for the high-side switches are not similar in eachphase as illustrated in Figure 7 dVdt occurs on theMOSFET drain when the MOSFET is already held in its offstate by the gate driver )e current created by this dVdt
Vin(t)G
G
VDD
VDDDBstrap1
DC source 5V
18V+
ndash
+ndash
C4C5
C6
C7
C8
C3
C2
Rdelay Rt
Roff Doff
CS-1CS-2CS-N
1st phase
2nd phase
ENIN
MOSFETdriver
R4 R5
R6
R2
R3
PWM-1 Q11
DC sourse
C1 R1
Optocoupler
Z1
Isolated area
Figure 6 Circuit schematic of gate driver circuit for Q11
2-Ph3-Ph4-Ph
5-Ph6-Ph
0
05
1
15
2
Nor
mal
ized
pk-
pk o
utpu
t cur
rent
ripp
le
01 02 03 040Duty cycle D
Figure 5 Normalized output inductor ripple versus duty cycle
Journal of Electrical and Computer Engineering 5
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
series-capacitor buck converter with automatic currentsharing
)e outline of the paper is as follows Section 2 describesthe fundamentals of this topology Section 3 derives themainparameters for the 2-pscB converter Section 4 describes theisolated gate driver circuit design Section 5 presents theproposed control scheme Section 6 presents the simulationresults using LTspice Section 7 shows the experimentalprototype and characterization results to illustrate thefunctionality and performance of the 2-pscB converterSections 8 and 9 provide discussion and the summary
2 Analysis of the 2-pscB Converter
A 2-pscB converter has four switching intervals the firstswitching interval D1T with Q11 and Q22 switching on thesecond and fourth switching intervalsD2Tand (1 minus d3)TwithQ12 and Q22 switching on and the third switching intervalD3T with Q12 and Q21 switching on Figure 1(b) shows thefour switching intervals and the switching devices that areswitched on during these intervals Hence
d2 minus d1( 1113857T D2T
d3 minus d2( 1113857T D3T
1 minus d3( 1113857T 1 minus D1 minus D2 minus D3( 1113857T
(1)
where T is the switching period At steady state during thefirst switching interval the high-side switch of phase Aswitch Q11 is switched on and the inductor current flowingthrough inductor L1 charges the series capacitor Cs [3 9])e duty cycle is given as
Vo
Vin
d1 d3 minus d2( 1113857
d1 + d3 minus d2
D1D3
D1 + D3 (2)
where d1 d2 and d3 represent switching intervals for theseries-capacitor buck modes When these intervals are thesame D1 D2 D3 D Hence
Vo
Vin
D
2 (3)
To achieve the current sharing balance between the twophases the switching voltage nodes must be the sameHence
Vcs
Vin
d1
d1 + d3 minus d2
D1
D1 + D3 (4)
From equations (2) and (4) at steady-state conditionsVo
Vcs D3 (5)
3 Derivation of Design Parameters
A new design approach for an automatic current sharingscheme is presented for the 2-pscB converter )e series-capacitor voltage is used to achieve current sharing be-tween phases without a current sensing circuit or externalcontrol loop as each phase inductor charges and dischargesthe series capacitor to maintain its average capacitorvoltage constant Design parameters are derived and ex-perimentally validated
)e main switches of both phases are driven at 180degphase shifts and with a duty ratio of less than 50 )einductor currents are defined as
IL1max min IR1plusmn
12
Vo
L11 minus D1( 1113857T1113890 1113891 IR1
plusmnΔiL1
2 (6)
IL2max min IR2plusmn
12
Vo
L21 minus D3( 1113857T1113890 1113891 IR2
plusmnΔiL2
2 (7)
where IL1max minand IL2max min
are the maximum andminimumvalues of phase A and B inductor currents IR1 and IR2 arethe average load currents at phase A and B respectively Inthis 2-pscB converter the total average output inductorcurrent is the sum of both the average phase inductorcurrents For a complete current sharing the peak-to-peakripple current of a single phase is
ΔiL1 ΔiL2
1L
Vin
2minus Vo1113874 1113875Ton1113876 1113877 (8)
vin
Q11
ndashiLCs
Cin
VCs
+
L2
Co
Q12
Q21
Q22
ioL1
RVo
+ndash
+
ndash
rCo
(a)
Q11 Q22
Q22
Q22
Q12
Q12 Q21
Q12
d1T
d2T
d3T
TTime (s)
Inte
rval
s
(b)
Figure 1 (a) Circuit schematic of the 2-pscB converter and (b) switching intervals
2 Journal of Electrical and Computer Engineering
where Ton D1T D3T As such a larger L and smaller Tonwill yield a smaller ripple current )e total average outputcurrent in terms of iL will be
Iout ILmax + ILmin
2 IR1
+ IR2 (9)
)e total inductor current at zero condition is equal tothe minimum value ILmin when Q11 is off in modes II andIV
ILmin iL(0) IL1min
+23IL2max
56Iout +
12
VoT
L
23
1 minus D3( 1113857 minus 1 minus D1( 11138571113876 1113877 (10)
When the load current contributed by each phase is atcomplete current sharing condition IR1
IR2 ( 12) Iout
the maximum inductor current value will be at full chargingof series capacitor in phase A and at fully discharging inphase B
ILmax iL d1T( 1113857 IL1max
+13IL2max
IR1+13IR2
+12
VoT
L
13
1 minus D3( 1113857 + 1 minus D1( 11138571113876 1113877
23Iout +
23
Vo
L( 1 minus D)T1113876 1113877
(11)
)us the peak-to-peak inductor current ripple is
ΔiL IL1maxminus IL1min
minus13IL2max
Vo
61
Lfsw5 minus 6D1 + D3( 1113857 minus
1R
1113888 1113889
56
Vo
L( 1 minus D)T1113876 1113877 minus
16Iout
16
5ΔiLphaseminus Iout1113876 1113877
(12)
where ΔiLphaseis phase A or B average current ripple at full
current sharing At continuous current mode (CCM) op-eration ILmin
is a positive value During current sharingwhen L1 L2 ILmin
gt 0 we have53IR1
minusVoT
L
1 minus d1( 1113857
2minus
d2 + 1 minus d3( 1113857
31113888 1113889gt 0 (13)
)e critical value for the two-phase inductors is then
Lcritical gtR
5fsw1 minus 3D1 + 2D3( 1113857 (14)
)e phase inductance should be within 15 to 2 timesthe critical inductance given in equation (14) to yield a goodefficiency Note that the efficiency of the converter in-creases with increasing inductance with performancedegradation in its transient response To avoid this effectthe inductance value should be chosen to provide
reasonable efficiency and good transient response As suchthe output inductor value can be expressed in terms of itscurrent ripple as
Lgt5R Vo (1 minus D)
fsw 6RΔiL + Vo1113858 1113859 (15)
)e instantaneous capacitor charge stored in one half ofthe switching period can be used to determine its outputcapacitance value as shown in Figure 2
ΔQ 12
T
41113874 1113875ΔiL2
CoΔVo (16a)
orΔVo
Vo
T
96Co
T
L5 minus 6D1 + D3( 1113857 minus
1R
1113874 1113875 (16b)
Hence during a complete current sharing
Co gt1
96fsw ΔVoVo( 1113857max
5Lfsw
(1 minus D) minus1R
1113888 1113889 (17)
Using the maximum and minimum output capacitorcurrent expressions
ΔiCo
1R + rCo
RΔiL minus Δvo( 1113857 (18)
For smaller output capacitor parasitic resistance rCoand
smaller Δvo ΔiCo ΔiL
Series-capacitor voltage VCs acts as an internal feedbackloop quantity to adjust the current sharing for the twophases As such if the inductor currents are not equal theseries-capacitor voltage would drift up or down and asmooth charging balance could not be maintained [16 17])is is because the average capacitor voltage remains con-stant only when the charge and discharging period balanceexists Inductor currents iL1 and iL2 charge and discharge theseries capacitor Cs respectively Figure 3 shows a simplifiedmathematical representation of 2-pscB converter with itsinternal current sharing mechanism resulting from the se-ries-capacitor voltage VCs including parasitic componentsIn steady-state conditions during automatic current sharingthe two inductor currents should be equal and then theaverage series capacitor voltage will be constant as well withapproximately half the input voltage across it and the seriescapacitor acts as a dc voltage source for the third intervalHence
Journal of Electrical and Computer Engineering 3
d1 Vin minus Vcs( 1113857 minus Vcs D3 0
Mode I langiCsrang langiL1rang
Mode II IV langiCsrang 0
Mode III langiCsrang minus langiL2rangwhere
langiCsrang langiL1rangD1 minus langiL2
rangD3 0
(19)
Using the iCs waveform shown in Figure 4 if IminD1 canbe neglected the minimum Cs value can be generalized andexpressed at complete current sharing as
ΔQ D1T IminD1 +12
D1TΔiL1
2 CsΔVCs (20)
Cs D1 Vo 1 minus D1( 1113857
4f2swL1 ΔVCs
+D1T IminD1
ΔVCs (21)
CsgtD2 ( 1 minus D)
4 L f2sw ΔVCsVCs( 1113857max
(22)
)e above equations enable design parameters such asCs Co and ∆iL to be determined
One of the technical advantages of multiphase is that thecombined output ripple (total ripple) is less than the ripplecurrent in each inductor (phase ripple) )is occurs due todriving the phases out of phase In case of the 2-pscBconverter at interleaving the phases with a proper timingcircuitry ripple current reductions can be easily achievedeven under unbalanced current sharing since the series-capacitor voltage can compensate for the current differencefor certain limits that results in much less output voltageripple Assuming all the ripple voltage is caused by thecapacitance of the output capacitor the approximated peakto the peak value of the total output current ripple to befiltered by the output capacitor is
ΔiL2pscB vo(1 minus 2D)
Lfsw
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)+
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)1113896 1113897 (23)
KRCM 2 1 minusm
NlowastD1113874 1113875(2m + 1 minus Nlowast2D) (24)
where KRCM is output current ripple cancellation multiplierN is the number of the phases and floor function returns thegreatest integer value less than the argument
m floor(NlowastD) (25)
where (m + 1)N geDgemN N gem ge 0Figure 5 shows that at certain duty cycle (D) value there
is a total cancellation of the ripple current according to theabove constraints For example total ripple current
cancellation for a 2-phase converter occurs beyond a dutycycle of 025 whereas for a 4-phase converter this totalripple current cancellation occurs at duty cycle beyond 0125and between a duty cycle of 025 and 0375 as shown inFigure 5
4 A Novel Isolated Gate Driver
Figure 6 shows the gate driver circuit using a UCC27531gate driver to accommodate adding a series capacitorbetween switches Q11 and Q12 of the phase A [18] where
iCo
(∆iL2) = (∆iCo2)
t
iComax
iComin
(12)d1T
D1T(32)d1T
Q
Figure 2 Instantaneous output capacitor circuit
+
+
+ndash
+
+
Control
++
+ndash
VoVin
IL1
IL2 IO
ICsVCs
D1
D3
Automatic current sharing
++
Figure 3 Self-balancing technique for 2-pscB converter
ΔvCsvin2
iCs
vCs
iminD3
imaxD3
imaxD1
T
ΔiL12
D1T D3T
ΔiL22t
t
Q
Q
Figure 4 Series-capacitor current and voltage at steady state
4 Journal of Electrical and Computer Engineering
the gate reference voltage for the isolated high-sideswitch is the positive side of Cs whereas the gate voltagefor the low-side switch circuit requires a different iso-lation loop since its reference voltage is ground As suchan isolation scheme must encompass the entire high-sideswitch circuit because inserting a series capacitor willintroduce a time delay between the gate voltages of thetwo switches
)is will interfere with the synchronization of theswitching time and voltage level Isolation scheme is re-quired to isolate the ground loops this means there shouldbe no direct conduction path between the high-side driverand the synchronous rectifier switch driver due to thevoltage storage element of Cs )e anode of bootstrap di-odes DBstrap1 is commonly connected to a driver sourceVDD)erefore bootstrap capacitors C5 to C8 are charged bya voltage difference between the driver source voltage VDDand the series-capacitor voltage VCs during the on-times ofthe Q12 switch through the bootstrap diode DBstrap1 Since
the four bootstraps diodes are isolated using an isolated DCsource the gate voltages of the main switches Q11 andQ21 areenough to charge the bootstrap capacitors As such phase Buses the same gate drivers as phase A To reduce the cost ofthe four matched bootstrap capacitors for each gate driverC5 to C8 two of them can be eliminated For voltage higherthan 12V external FETs are used for better heat distributionand isolation [15] )e gate driver should be located as closeto the MOSFETs as possible In this way self-inductance andself-resistance of the traces will be reduced to minimizevoltage spikes and reduce EMI For a complete currentsharing dead time must be the same for both phases In theproposed circuit there are two ways to adjust the dead timebetween the high-side signal and low-side signal using twovariable resistors before and after the optocoupler Currentsink loops for the high-side switches are not similar in eachphase as illustrated in Figure 7 dVdt occurs on theMOSFET drain when the MOSFET is already held in its offstate by the gate driver )e current created by this dVdt
Vin(t)G
G
VDD
VDDDBstrap1
DC source 5V
18V+
ndash
+ndash
C4C5
C6
C7
C8
C3
C2
Rdelay Rt
Roff Doff
CS-1CS-2CS-N
1st phase
2nd phase
ENIN
MOSFETdriver
R4 R5
R6
R2
R3
PWM-1 Q11
DC sourse
C1 R1
Optocoupler
Z1
Isolated area
Figure 6 Circuit schematic of gate driver circuit for Q11
2-Ph3-Ph4-Ph
5-Ph6-Ph
0
05
1
15
2
Nor
mal
ized
pk-
pk o
utpu
t cur
rent
ripp
le
01 02 03 040Duty cycle D
Figure 5 Normalized output inductor ripple versus duty cycle
Journal of Electrical and Computer Engineering 5
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
where Ton D1T D3T As such a larger L and smaller Tonwill yield a smaller ripple current )e total average outputcurrent in terms of iL will be
Iout ILmax + ILmin
2 IR1
+ IR2 (9)
)e total inductor current at zero condition is equal tothe minimum value ILmin when Q11 is off in modes II andIV
ILmin iL(0) IL1min
+23IL2max
56Iout +
12
VoT
L
23
1 minus D3( 1113857 minus 1 minus D1( 11138571113876 1113877 (10)
When the load current contributed by each phase is atcomplete current sharing condition IR1
IR2 ( 12) Iout
the maximum inductor current value will be at full chargingof series capacitor in phase A and at fully discharging inphase B
ILmax iL d1T( 1113857 IL1max
+13IL2max
IR1+13IR2
+12
VoT
L
13
1 minus D3( 1113857 + 1 minus D1( 11138571113876 1113877
23Iout +
23
Vo
L( 1 minus D)T1113876 1113877
(11)
)us the peak-to-peak inductor current ripple is
ΔiL IL1maxminus IL1min
minus13IL2max
Vo
61
Lfsw5 minus 6D1 + D3( 1113857 minus
1R
1113888 1113889
56
Vo
L( 1 minus D)T1113876 1113877 minus
16Iout
16
5ΔiLphaseminus Iout1113876 1113877
(12)
where ΔiLphaseis phase A or B average current ripple at full
current sharing At continuous current mode (CCM) op-eration ILmin
is a positive value During current sharingwhen L1 L2 ILmin
gt 0 we have53IR1
minusVoT
L
1 minus d1( 1113857
2minus
d2 + 1 minus d3( 1113857
31113888 1113889gt 0 (13)
)e critical value for the two-phase inductors is then
Lcritical gtR
5fsw1 minus 3D1 + 2D3( 1113857 (14)
)e phase inductance should be within 15 to 2 timesthe critical inductance given in equation (14) to yield a goodefficiency Note that the efficiency of the converter in-creases with increasing inductance with performancedegradation in its transient response To avoid this effectthe inductance value should be chosen to provide
reasonable efficiency and good transient response As suchthe output inductor value can be expressed in terms of itscurrent ripple as
Lgt5R Vo (1 minus D)
fsw 6RΔiL + Vo1113858 1113859 (15)
)e instantaneous capacitor charge stored in one half ofthe switching period can be used to determine its outputcapacitance value as shown in Figure 2
ΔQ 12
T
41113874 1113875ΔiL2
CoΔVo (16a)
orΔVo
Vo
T
96Co
T
L5 minus 6D1 + D3( 1113857 minus
1R
1113874 1113875 (16b)
Hence during a complete current sharing
Co gt1
96fsw ΔVoVo( 1113857max
5Lfsw
(1 minus D) minus1R
1113888 1113889 (17)
Using the maximum and minimum output capacitorcurrent expressions
ΔiCo
1R + rCo
RΔiL minus Δvo( 1113857 (18)
For smaller output capacitor parasitic resistance rCoand
smaller Δvo ΔiCo ΔiL
Series-capacitor voltage VCs acts as an internal feedbackloop quantity to adjust the current sharing for the twophases As such if the inductor currents are not equal theseries-capacitor voltage would drift up or down and asmooth charging balance could not be maintained [16 17])is is because the average capacitor voltage remains con-stant only when the charge and discharging period balanceexists Inductor currents iL1 and iL2 charge and discharge theseries capacitor Cs respectively Figure 3 shows a simplifiedmathematical representation of 2-pscB converter with itsinternal current sharing mechanism resulting from the se-ries-capacitor voltage VCs including parasitic componentsIn steady-state conditions during automatic current sharingthe two inductor currents should be equal and then theaverage series capacitor voltage will be constant as well withapproximately half the input voltage across it and the seriescapacitor acts as a dc voltage source for the third intervalHence
Journal of Electrical and Computer Engineering 3
d1 Vin minus Vcs( 1113857 minus Vcs D3 0
Mode I langiCsrang langiL1rang
Mode II IV langiCsrang 0
Mode III langiCsrang minus langiL2rangwhere
langiCsrang langiL1rangD1 minus langiL2
rangD3 0
(19)
Using the iCs waveform shown in Figure 4 if IminD1 canbe neglected the minimum Cs value can be generalized andexpressed at complete current sharing as
ΔQ D1T IminD1 +12
D1TΔiL1
2 CsΔVCs (20)
Cs D1 Vo 1 minus D1( 1113857
4f2swL1 ΔVCs
+D1T IminD1
ΔVCs (21)
CsgtD2 ( 1 minus D)
4 L f2sw ΔVCsVCs( 1113857max
(22)
)e above equations enable design parameters such asCs Co and ∆iL to be determined
One of the technical advantages of multiphase is that thecombined output ripple (total ripple) is less than the ripplecurrent in each inductor (phase ripple) )is occurs due todriving the phases out of phase In case of the 2-pscBconverter at interleaving the phases with a proper timingcircuitry ripple current reductions can be easily achievedeven under unbalanced current sharing since the series-capacitor voltage can compensate for the current differencefor certain limits that results in much less output voltageripple Assuming all the ripple voltage is caused by thecapacitance of the output capacitor the approximated peakto the peak value of the total output current ripple to befiltered by the output capacitor is
ΔiL2pscB vo(1 minus 2D)
Lfsw
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)+
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)1113896 1113897 (23)
KRCM 2 1 minusm
NlowastD1113874 1113875(2m + 1 minus Nlowast2D) (24)
where KRCM is output current ripple cancellation multiplierN is the number of the phases and floor function returns thegreatest integer value less than the argument
m floor(NlowastD) (25)
where (m + 1)N geDgemN N gem ge 0Figure 5 shows that at certain duty cycle (D) value there
is a total cancellation of the ripple current according to theabove constraints For example total ripple current
cancellation for a 2-phase converter occurs beyond a dutycycle of 025 whereas for a 4-phase converter this totalripple current cancellation occurs at duty cycle beyond 0125and between a duty cycle of 025 and 0375 as shown inFigure 5
4 A Novel Isolated Gate Driver
Figure 6 shows the gate driver circuit using a UCC27531gate driver to accommodate adding a series capacitorbetween switches Q11 and Q12 of the phase A [18] where
iCo
(∆iL2) = (∆iCo2)
t
iComax
iComin
(12)d1T
D1T(32)d1T
Q
Figure 2 Instantaneous output capacitor circuit
+
+
+ndash
+
+
Control
++
+ndash
VoVin
IL1
IL2 IO
ICsVCs
D1
D3
Automatic current sharing
++
Figure 3 Self-balancing technique for 2-pscB converter
ΔvCsvin2
iCs
vCs
iminD3
imaxD3
imaxD1
T
ΔiL12
D1T D3T
ΔiL22t
t
Q
Q
Figure 4 Series-capacitor current and voltage at steady state
4 Journal of Electrical and Computer Engineering
the gate reference voltage for the isolated high-sideswitch is the positive side of Cs whereas the gate voltagefor the low-side switch circuit requires a different iso-lation loop since its reference voltage is ground As suchan isolation scheme must encompass the entire high-sideswitch circuit because inserting a series capacitor willintroduce a time delay between the gate voltages of thetwo switches
)is will interfere with the synchronization of theswitching time and voltage level Isolation scheme is re-quired to isolate the ground loops this means there shouldbe no direct conduction path between the high-side driverand the synchronous rectifier switch driver due to thevoltage storage element of Cs )e anode of bootstrap di-odes DBstrap1 is commonly connected to a driver sourceVDD)erefore bootstrap capacitors C5 to C8 are charged bya voltage difference between the driver source voltage VDDand the series-capacitor voltage VCs during the on-times ofthe Q12 switch through the bootstrap diode DBstrap1 Since
the four bootstraps diodes are isolated using an isolated DCsource the gate voltages of the main switches Q11 andQ21 areenough to charge the bootstrap capacitors As such phase Buses the same gate drivers as phase A To reduce the cost ofthe four matched bootstrap capacitors for each gate driverC5 to C8 two of them can be eliminated For voltage higherthan 12V external FETs are used for better heat distributionand isolation [15] )e gate driver should be located as closeto the MOSFETs as possible In this way self-inductance andself-resistance of the traces will be reduced to minimizevoltage spikes and reduce EMI For a complete currentsharing dead time must be the same for both phases In theproposed circuit there are two ways to adjust the dead timebetween the high-side signal and low-side signal using twovariable resistors before and after the optocoupler Currentsink loops for the high-side switches are not similar in eachphase as illustrated in Figure 7 dVdt occurs on theMOSFET drain when the MOSFET is already held in its offstate by the gate driver )e current created by this dVdt
Vin(t)G
G
VDD
VDDDBstrap1
DC source 5V
18V+
ndash
+ndash
C4C5
C6
C7
C8
C3
C2
Rdelay Rt
Roff Doff
CS-1CS-2CS-N
1st phase
2nd phase
ENIN
MOSFETdriver
R4 R5
R6
R2
R3
PWM-1 Q11
DC sourse
C1 R1
Optocoupler
Z1
Isolated area
Figure 6 Circuit schematic of gate driver circuit for Q11
2-Ph3-Ph4-Ph
5-Ph6-Ph
0
05
1
15
2
Nor
mal
ized
pk-
pk o
utpu
t cur
rent
ripp
le
01 02 03 040Duty cycle D
Figure 5 Normalized output inductor ripple versus duty cycle
Journal of Electrical and Computer Engineering 5
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
d1 Vin minus Vcs( 1113857 minus Vcs D3 0
Mode I langiCsrang langiL1rang
Mode II IV langiCsrang 0
Mode III langiCsrang minus langiL2rangwhere
langiCsrang langiL1rangD1 minus langiL2
rangD3 0
(19)
Using the iCs waveform shown in Figure 4 if IminD1 canbe neglected the minimum Cs value can be generalized andexpressed at complete current sharing as
ΔQ D1T IminD1 +12
D1TΔiL1
2 CsΔVCs (20)
Cs D1 Vo 1 minus D1( 1113857
4f2swL1 ΔVCs
+D1T IminD1
ΔVCs (21)
CsgtD2 ( 1 minus D)
4 L f2sw ΔVCsVCs( 1113857max
(22)
)e above equations enable design parameters such asCs Co and ∆iL to be determined
One of the technical advantages of multiphase is that thecombined output ripple (total ripple) is less than the ripplecurrent in each inductor (phase ripple) )is occurs due todriving the phases out of phase In case of the 2-pscBconverter at interleaving the phases with a proper timingcircuitry ripple current reductions can be easily achievedeven under unbalanced current sharing since the series-capacitor voltage can compensate for the current differencefor certain limits that results in much less output voltageripple Assuming all the ripple voltage is caused by thecapacitance of the output capacitor the approximated peakto the peak value of the total output current ripple to befiltered by the output capacitor is
ΔiL2pscB vo(1 minus 2D)
Lfsw
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)+
N(D minus (mN))(((2m + 1)N) minus 2D)
D((12) minus D)1113896 1113897 (23)
KRCM 2 1 minusm
NlowastD1113874 1113875(2m + 1 minus Nlowast2D) (24)
where KRCM is output current ripple cancellation multiplierN is the number of the phases and floor function returns thegreatest integer value less than the argument
m floor(NlowastD) (25)
where (m + 1)N geDgemN N gem ge 0Figure 5 shows that at certain duty cycle (D) value there
is a total cancellation of the ripple current according to theabove constraints For example total ripple current
cancellation for a 2-phase converter occurs beyond a dutycycle of 025 whereas for a 4-phase converter this totalripple current cancellation occurs at duty cycle beyond 0125and between a duty cycle of 025 and 0375 as shown inFigure 5
4 A Novel Isolated Gate Driver
Figure 6 shows the gate driver circuit using a UCC27531gate driver to accommodate adding a series capacitorbetween switches Q11 and Q12 of the phase A [18] where
iCo
(∆iL2) = (∆iCo2)
t
iComax
iComin
(12)d1T
D1T(32)d1T
Q
Figure 2 Instantaneous output capacitor circuit
+
+
+ndash
+
+
Control
++
+ndash
VoVin
IL1
IL2 IO
ICsVCs
D1
D3
Automatic current sharing
++
Figure 3 Self-balancing technique for 2-pscB converter
ΔvCsvin2
iCs
vCs
iminD3
imaxD3
imaxD1
T
ΔiL12
D1T D3T
ΔiL22t
t
Q
Q
Figure 4 Series-capacitor current and voltage at steady state
4 Journal of Electrical and Computer Engineering
the gate reference voltage for the isolated high-sideswitch is the positive side of Cs whereas the gate voltagefor the low-side switch circuit requires a different iso-lation loop since its reference voltage is ground As suchan isolation scheme must encompass the entire high-sideswitch circuit because inserting a series capacitor willintroduce a time delay between the gate voltages of thetwo switches
)is will interfere with the synchronization of theswitching time and voltage level Isolation scheme is re-quired to isolate the ground loops this means there shouldbe no direct conduction path between the high-side driverand the synchronous rectifier switch driver due to thevoltage storage element of Cs )e anode of bootstrap di-odes DBstrap1 is commonly connected to a driver sourceVDD)erefore bootstrap capacitors C5 to C8 are charged bya voltage difference between the driver source voltage VDDand the series-capacitor voltage VCs during the on-times ofthe Q12 switch through the bootstrap diode DBstrap1 Since
the four bootstraps diodes are isolated using an isolated DCsource the gate voltages of the main switches Q11 andQ21 areenough to charge the bootstrap capacitors As such phase Buses the same gate drivers as phase A To reduce the cost ofthe four matched bootstrap capacitors for each gate driverC5 to C8 two of them can be eliminated For voltage higherthan 12V external FETs are used for better heat distributionand isolation [15] )e gate driver should be located as closeto the MOSFETs as possible In this way self-inductance andself-resistance of the traces will be reduced to minimizevoltage spikes and reduce EMI For a complete currentsharing dead time must be the same for both phases In theproposed circuit there are two ways to adjust the dead timebetween the high-side signal and low-side signal using twovariable resistors before and after the optocoupler Currentsink loops for the high-side switches are not similar in eachphase as illustrated in Figure 7 dVdt occurs on theMOSFET drain when the MOSFET is already held in its offstate by the gate driver )e current created by this dVdt
Vin(t)G
G
VDD
VDDDBstrap1
DC source 5V
18V+
ndash
+ndash
C4C5
C6
C7
C8
C3
C2
Rdelay Rt
Roff Doff
CS-1CS-2CS-N
1st phase
2nd phase
ENIN
MOSFETdriver
R4 R5
R6
R2
R3
PWM-1 Q11
DC sourse
C1 R1
Optocoupler
Z1
Isolated area
Figure 6 Circuit schematic of gate driver circuit for Q11
2-Ph3-Ph4-Ph
5-Ph6-Ph
0
05
1
15
2
Nor
mal
ized
pk-
pk o
utpu
t cur
rent
ripp
le
01 02 03 040Duty cycle D
Figure 5 Normalized output inductor ripple versus duty cycle
Journal of Electrical and Computer Engineering 5
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
the gate reference voltage for the isolated high-sideswitch is the positive side of Cs whereas the gate voltagefor the low-side switch circuit requires a different iso-lation loop since its reference voltage is ground As suchan isolation scheme must encompass the entire high-sideswitch circuit because inserting a series capacitor willintroduce a time delay between the gate voltages of thetwo switches
)is will interfere with the synchronization of theswitching time and voltage level Isolation scheme is re-quired to isolate the ground loops this means there shouldbe no direct conduction path between the high-side driverand the synchronous rectifier switch driver due to thevoltage storage element of Cs )e anode of bootstrap di-odes DBstrap1 is commonly connected to a driver sourceVDD)erefore bootstrap capacitors C5 to C8 are charged bya voltage difference between the driver source voltage VDDand the series-capacitor voltage VCs during the on-times ofthe Q12 switch through the bootstrap diode DBstrap1 Since
the four bootstraps diodes are isolated using an isolated DCsource the gate voltages of the main switches Q11 andQ21 areenough to charge the bootstrap capacitors As such phase Buses the same gate drivers as phase A To reduce the cost ofthe four matched bootstrap capacitors for each gate driverC5 to C8 two of them can be eliminated For voltage higherthan 12V external FETs are used for better heat distributionand isolation [15] )e gate driver should be located as closeto the MOSFETs as possible In this way self-inductance andself-resistance of the traces will be reduced to minimizevoltage spikes and reduce EMI For a complete currentsharing dead time must be the same for both phases In theproposed circuit there are two ways to adjust the dead timebetween the high-side signal and low-side signal using twovariable resistors before and after the optocoupler Currentsink loops for the high-side switches are not similar in eachphase as illustrated in Figure 7 dVdt occurs on theMOSFET drain when the MOSFET is already held in its offstate by the gate driver )e current created by this dVdt
Vin(t)G
G
VDD
VDDDBstrap1
DC source 5V
18V+
ndash
+ndash
C4C5
C6
C7
C8
C3
C2
Rdelay Rt
Roff Doff
CS-1CS-2CS-N
1st phase
2nd phase
ENIN
MOSFETdriver
R4 R5
R6
R2
R3
PWM-1 Q11
DC sourse
C1 R1
Optocoupler
Z1
Isolated area
Figure 6 Circuit schematic of gate driver circuit for Q11
2-Ph3-Ph4-Ph
5-Ph6-Ph
0
05
1
15
2
Nor
mal
ized
pk-
pk o
utpu
t cur
rent
ripp
le
01 02 03 040Duty cycle D
Figure 5 Normalized output inductor ripple versus duty cycle
Journal of Electrical and Computer Engineering 5
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
charges the Cgd Miller capacitance and is shunted by thepull-down stage of the driver
If the pull-down impedance is not sufficiently low then avoltage spike can appear in the Vgs of the MOSFET )eupper limit for the voltage at the EN node is 5V )iscomplete gate circuit contains 4 bootstrap diodes at theoutput terminals of the power supply fly-back transformer
5 An I2 Control Scheme for 2-pscB Converter
)e objective of the feedback compensation loop is to enableits closed-loop converter to possess adequate line and loadregulations with a low output voltage overshoot Multiphasecurrent sharing two loops control was proposed in [19 20]Converter control to output transfer function at full currentsharing is
Gv D(s) R
2R + rL
vin sωempty( 1113857 + 1( 1113857
s2ω2o( 1113857 + sQoωo( 1113857 + 1
(26)
where
ωempty R
CorCo
ωo
2R + rL
LCo R + rCo( 1113857
1113971
(27)
Qo
LCo 2R + rL( 1113857 R + rCo( 1113857
1113969
L + RCorL + CorCo rL + 2RCorCo( 1113857 (28)
To obtain a well-regulated average output voltage signalswitching frequency must be greater than ten times theresonant frequency for small output voltage ripple(fsw asymp 20fo recommended) )e natural output impedance(Zout) of output filter peaks at the converter resonant fre-quency (fo 12 kHz) )erefore the unity-gain crossoverfrequency (fc) must be higher than the resonance frequencyto yield a sufficient gain margin to suppress its ringing effectmaintain constant series-capacitor voltage and obtain asufficient phase margin If the equivalent series resistance(ESR) of the capacitor that dominates its impedance at
higher frequencies is neglected then the peak resonanceoccurs at
Zoutminus Max1113868111386811138681113868
1113868111386811138681113868 R
2Z2
o + r2L
2Z2o( 1113857 Z2
o + RrL( 11138572
+ r2L
1113971
(29)
where Zo LCo
1113968is the characteristic impedance of the
filterFor a converter that has a long series capacitance
charging period an enhanced I2 current control scheme isused to compare the sum of the output current (with acurrent sensing gain Zi) and analog current of its outputvoltage feedback line (with a current sensing gain Zv) to theoutput voltage of the compensated error amplifier )eenhanced I2 control can achieve a fast load transient re-sponse at a constant frequency )e equivalence series re-sistance (ESR) of the output capacitors or iL is used as thecurrent sensing resistor as shown in Figure 8(a) where theinner loop uses the inverting input signal voltage Vsenseacross the sensing resistor Rs generated by both outputcurrent io and feedback as a proportional feedback controlvariable and the outer loop uses the control signal VCgenerated by compensating the errors between the outputvoltage vo and the reference voltage Vref in the error am-plifier )e sensing voltage Vsense in the inner loop containsthe information of both the feedback output voltage andinductor current when Vsense reaches the value of VC )ecomparator changes the state at its output u(t) whichcompares with the oscillator ramp signal r(t) at twice theswitching frequency )is allows the logic latch circuit togenerate two pulses at half the oscillator frequency)e logiclatch and delay time circuit consist of logic gates and gal-vanic isolation of (10ndash50)MBd to produce four signals with amaximum 50 duty cycle that can be controlled by onlyDDrive signal variations An RC inverting negative feedbackcircuit can be added to the current regulator (comparator) toaccurately control the overall current regulator gain )eerror amplifier uses a PID compensator with a Vref of 125V
A single feedback control loop with one modulator forthe two phases gives several advantages over conventionalschemes [7 13 19] such as immunity against sensinginaccuracies which potentially reduces the complexity and
RGoff
Gate driver
Zener diode ofdriver voltage
Q11
vDS
Coss
CDG
CGS
Csn
Ci
vin
Isink
ROL
2nd phase
(a)
RGoff
Gate driver
Zener diode ofdriver voltage
Q12
vDS
Coss
CDG
CGS
Ci
vCs
Isink
ROL
(b)
Figure 7 Phase A current sink loops (a) top switch and (b) bottom switch
6 Journal of Electrical and Computer Engineering
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
the number of components and size of the controller andminimizes the time propagation delay and voltage drop toenable the generation of two duty cycle pulses D1 and D3within one ramp signal period As such no offline or onlinecalibration is needed to achieve optimum efficiencyFigure 8(b) shows the waveforms within the compensatorloop where xprime(t)≜1 minus x(t) yprime(t)≜1 minus y(t)
As shown in Figure 9 the ramp signal frequency istwice the converter switching frequency to generate two-phase pulses During a step response the controller de-creases the current passing through the load to minimizethe current surge as seen in Figure 10(a) As can be seen alow overshoot voltage is due to fast-direct feedback loopaction where series-capacitor charging starts instanta-neously at zero time at the same time its soft start featureallows the output voltage to ramp up in a controlledmanner minimizing output voltage overshoot duringstartup as shown in Figure 10(b) )e step response hasonly a small effect on maintaining automatic currentsharing balance as shown in Figure 10(c) where iL1 isdecreased by switching off Q11 to achieve a predeterminedovershoot voltage magnitude as well as to enable the softstart feature As such it eliminates the need to monitorand precharge the series-capacitor voltage )e simulatedMatlab waveforms shown in Figure 10 verify the analyticaland design methods
6 Simulation Work
Using derived equations (12) to (22) the converter pa-rameters for the desired load and output ripples are de-termined )e specifications for the 11012V dc 2-pscBconverter are listed in Table 1 A two-phase series-capacitorbuck converter is simulated using LTspice )e simulationefficiency reaches 987 for a perfect dead time imple-mentation in the steady-state operation
Figure 11(a) shows the waveforms for Vds and Ids of Q11during theD1T interval As can be seen both Vds andVCs are55V Its drain current which is also the phase A inductorcurrent increases linearly to charge the series capacitor to itsmaximum voltage Figure 11(b) shows the switching lossesofQ11Current spikes occur during the switching transitionsof both Q11 and Q22 )e total switching losses are 40Wduring a 4 ns switching period Figure 11(c) shows Ig wherethe gate currents are less than 15A and 25A during therising and falling edges of the gate pulses
Figure 12 shows the series-capacitor voltage currentand two-phase inductor current waveforms during steady-
+
ndash+p
ndashn
u(t)
r(t)+ ndash
+ ndash
ndashiLCsVCs
+
L2
CoQ12
Q21
Qt
voL1
Latc
h an
d de
ad
time C
ircui
t
vo
VPP
ZiZC
ZFBVrefV
CCo
RCo
Rs
Com
pane
sato
r
rC
Io
Voltage regulator
Current regulator
Sensinganalog conditioning
Isolated gate drivers
(T = 1Fsw)DDrive
VDDrive
++
Zv
x(t)
xprime(t)
y(t)
yprime(t)
Current sense Amp gain
(T = 05 Fsw)
Q11
vin(t)
VsenseVC
Com
pens
ator
(a)
V() V(ref)
V(u) V(r)
V(Ddrive)
Vgs(Q11) Vgs(Q12)
Vgs(Q21) Vgs(Q22)
12501V12499V12497V
14V6V
ndash2V
40V20V00V
16V
ndash2V
16V
ndash2V27720ms 27741ms
Time (s)27762ms 27783ms
10V4V
7V
(b)
Figure 8 Enhanced I2 control scheme (a) circuit and (b) waveforms of the control parameters
D1T
D3T
T
T2
Vc
DDrive (T2) DDrive (T2)
U
VPP
U
VDD
DDrive = (VPP ndash U)VPP
t
t
t
t
VDD
Figure 9 Generation of the control pulses DDrive
Journal of Electrical and Computer Engineering 7
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
Step load340A
40A30A20A10A00A
318A296A
(a)
132V124V116V
175ms 196ms 217ms 238ms
Vo
16V12V
8V4V0V
(b)
00ms 03ms 06ms 09ms 12ms 15ms
Time (s)
18ms 21ms 24ms
IL1 IL2
42A24A
ndash12Andash30A
6A
(c)
Figure 10 Simulated transient response with (a) step load (b) output voltage and (c) inductor currents of the converter
Table 1 2-pscB converter experimental evaluation parameters
Component Abbreviation ValueSeries capacitor Cs 9 μFPhase inductors L1 and L2 10 μHOutput capacitor Co gt80 μFSwitching frequency Fsw 250 kHzInput voltage Vin 110VOutput voltage Vo 125ndash135VStray components rCs 20mΩStray components ron rL1 rL2 lt20mΩOutput power Po lt75W
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11) Id (Q11)
ndash6V
0V
6V
12V
18V
24V
30V
36V
42V
48V
54V
60V
ndash2A
0A
2A
4A
6A
(a)
Figure 11 Continued
8 Journal of Electrical and Computer Engineering
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
state operation As can be seen from Figure 12(a) the av-erage VCs maintains its value at exactly half of the inputvoltage with a voltage ripple of less than 05V )e outputvoltage ripple can be controlled by the size of the outputfilter )e average charging and discharging currents for theseries capacitor are similar as shown in Figure 12(b) thisverifies the steady-state operation of the 2-pscB converterFigure 12(c) shows the inductor currents iL1 and iL2 the twoinductor currents have identical magnitudes and they are180deg out of phase at steady-state operation
7 Experimental Results
)e component selections for the 2-pscB converter are firstjustified For a 254 cm long and 40-mil wide printed circuitboard (PCB) copper trace the parasitic inductance is about 8nH)e parasitic inductance of a 04mm diameter via a 16mmthick PCB is 12nH [21 22])e self-resistance calculations of alltraces are performed using the Autodesk Eagle software )e
parasitic resistance rCs can be reduced to half the value by usingtwo parallel aluminum electrolytic capacitors of 45microF with adissipation factor of 03 for the two series capacitors Cs1 and Cs2)e total ESR of the two parallel capacitors is
ESR tan δ2ωCs
002Ω at 250 kHz (30)
Two ERU (16) helically wound choke inductors with aDC resistance of 37mΩ and a current saturation of 183Aare used for the phase inductors A total of fourIPB530N15N3 power MOSFETs are required to implementthe 2-pscB and an additional power MOSFET (Si7898) isused for the fly-back converter to provide or serve as acomponent power supply as shown in Table 2 [23]
)is fly-back converter is used to supply four isolated18V to drive the gate of four MOSFETs at a frequency of323 kHz A Tektronix P5200 Differential Probe 50X500Xattenuation was used to measure voltages as shown in
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms
Vds (Q11)lowastId (Q11)
ndash40W
0W
40W
80W
120W
160W
200W
240W
280W
320W
360W
400W
440W
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash21A
ndash18A
ndash15A
ndash12A
ndash09A
ndash06A
ndash03A
00A
03A
06A
09A
12A
15A
(c)
Figure 11 Waveforms of (a) Vds and Id of Q11 (b) switching losses of Q11 and (c) gate current (source and sink) Ig of Q11
Journal of Electrical and Computer Engineering 9
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357ms5480 V
5484 V
5488 V
5492 V
5496 V
5500 V
5504 V
5508 V
5512 V
5516 V
5520 VV (Q11_S SW1)
(a)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash6 A
ndash5 A
ndash4 A
ndash3 A
ndash2 A
ndash1 A
0 A
1 A
2 A
3 A
4 A
5 AI (Cs_2) + I (Cs_1)
(b)
1346ms 1347ms 1348ms 1349ms 1350ms 1351ms 1352ms 1353ms 1354ms 1355ms 1356ms 1357msndash04 A
00 A
04 A
08 A
12 A
16 A
20 A
24 A
28 A
32 A
36 A
40 A
(c)
Figure 12 Waveforms of (a) series-capacitor voltage VCs (b) series-capacitor current ICs and (c) inductor currents IL1 and IL2
10 Journal of Electrical and Computer Engineering
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
Figure 13 )e evaluation model (EVM ) input 5 V PWMsignal with twice the switching frequency and a double dutycycle to generate four signals through the latch circuit Inputsignal and phase A generated gate driver signals are shown inFigure 14 )e input PWM signal (DDrive) will be at 500 kHzat 50 duty or less to generate four signals at 250 kHz at 25duty cycle or less As such controlling the four gate signalsbecomes easier and can be achieved with only themain input
PWM signal Signal delay time between the optocouplerinput and MOSFET gate is measured to be 170 ns whichincludes the rise time and first propagation delay time asshown in Figure 15 )e time delay is 57 ns to include boththe fall and second propagation delay times )is differenceis caused by the PCB conductors which can be reduced by abetter PCB layout as well as a multilayer structure to separatethe power conductors from the ground conductors Toachieve the required dVdt the gate driver must deliver thegate charge Qgd in 20 ns or less )is means a gate current ofIg = 3 nC20 ns = 015A or higher is needed However theMOSFET gate-source current reaches 12 A and the sinkcurrent is less (Qgd = 3 nC maximum dVdsdt= 20Vns) asshown in Figure 16 which is almost similar to the simulatedgate current value for a Rg(on) (ext) = 2Ω Rg(off) (ext) = 0(Figure 11(c)) Figure 17 exhibits the typical waveforms ofVds versus Vgs for MOSFET Q21 of phase B Figure 18 showsthe node voltages Vsw1 and Vsw2 at a switching frequency of250 kHz As can be seen these node voltages have a variationof within 05V As stated earlier these node voltages must bethe same at full current sharing Any difference or any smallvariation is caused by dead time trace width and lengthunbalance of the two phase paths or it can be the result ofswitching speed due to the different charging and dis-charging time for the MOSFETrsquos input capacitors (Cgs)Since the switch node voltage slope is caused by the loadcurrent as such the slope of Vsw1 is affected by the chargingperiod of both Cs and Co )is is because Vsw2 charges onlyCo and then a slope difference can be seen To eliminate thisdifference the value of Cs must be chosen carefully in termsof inductance variations zero dc bias inductance saturationprofiles and converter layout and Cs position
Figures 19 and 20 show the series-capacitor current iCsand inductor currents iL1 and iL2 at a resistive load currentof 24 A respectively )e phase A inductor current (iL1) hasa slightly higher peak-to-peak ripple due possibly to slopedifference and converter layout parasitic inductance )e
Table 2 2-pscB converter MOSFETs
MOSFET Ciss VDS RDS (on)max IDIPB530N15N3 667 pF 150 V 53 mΩ 21 ASi7898 (fly-back) 900 pF 150 V 85 mΩ 48 A
Vgs (Fly-backMOSFET)
Vds (Fly-backMOSFET)
5Vdiv
1μsdiv
05 times 50Vdiv
Figure 13 Fly-back gate driver signal Vgs (top waveform) anddrain source voltage Vds (bottom waveform) at the transformerinput
Input PWM
Vgs (Q11) Vgs (Q12)
02 times 50Vdiv
5Vdiv
Figure 14 Input PWM signalDDrive (top waveform) and the gate-source voltages of Q11 and Q12 (bottom waveforms)
1Vdiv
OptocouplerPWM signal
10VdivVgs Q11
Figure 15 Signal delay between the optocoupler PWM input signaland the gate-source voltage of Q11
Journal of Electrical and Computer Engineering 11
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
maximum efficiency achieved from this prototype converteris 92 at a load current of 338A and an input current of442mA despite the peak-to-peak ripple of about 270mA dueto charging and discharging of both Cs and Co Prototype isshown in Figure 21 Maximum output power of 73W withan efficiency of 91was achieved at a full load current of 6A)e experimental and simulated efficiency results are il-lustrated in Figure 22
8 Discussion
Due to PCB trace drop voltages and layout mismatch ofthe two phases there is an expected small variation be-tween the simulation and measured efficiency resultsMoreover wires and component parasitic circuit elementsalso have a negative impact Dissipation curves show a
normal increase with increasing load currents Eventhough there is a small trace resistive unbalance betweenthe two phases its current sharing mechanism is stillfunctioning well Because of the above the node voltage atVsw2 is nearly 05 V less than that at Vsw1 Otherwiselosses are very low when current sharing condition isachieved For some cases to reduce losses and provideprotection to the MOSFET switches there is a need to addtime delay control circuit to precharge the series capacitorto half of its nominal voltage to protect the converter andreduce the charging current surge before switching on theconverter
Using only one PWM signal input of the latch logiccircuit may give an advantage for the closed-loop circuit andsimplify the control scheme where the control loop fre-quency and duty cycle should be twice the actual switching
Vgs (Q12) before Rg 10Vdiv
Ig (sink current)15AdivIg (source current)
Vgs (Q12) aer Rg 10Vdiv
Figure 16 Gate-source voltages of Q12 measured before gate resistor Rg (top waveform) and after Rg (bottom waveform)
Vds Q21
Vgs Q21
1μsdiv05 times 50Vdiv
05 times 50Vdiv
Figure 17 Typical waveforms of Vds and Vgs for Q21
12 Journal of Electrical and Computer Engineering
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
Vgs_Q11
1microsdiv
Vsw1
Vsw2
05 times 50Vdiv
Figure 18 Gate pulses of Q11 (top waveform) and Vsw1 and Vsw2 at 250 kHz (bottom waveforms)
Vgs_Q11
05 times 50Vdiv
ICs
02 times 50Adiv 1μsdiv
Figure 19 Series-capacitor current ICs at 250 kHz
Vgs Q11
IL2 IL1
Vgs Q21
05 times 50Vdiv
2Adiv2Adiv
1μsdiv
Figure 20 Inductor currents IL1 and IL2 at a load current of 24 A
Journal of Electrical and Computer Engineering 13
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
frequency Since the main switches of both the phases aredriven at 180o phase shift and with a duty ratio of less than50 a push-pull controller can be implemented to achievethis range Note that the other two MOSFETs for the syn-chronous rectifier switches (lower side) are just comple-mentary switches According to Amperersquos Law the physicalphase current loop forms a magnetic field in proportion tothe output shared current and the phase loop area )is fieldcan couple with other circuit loops such as control circuit(per Faradayrsquos law) with more coupling at higher frequen-cies resulting in harmful crosstalk But this is not the case ofthis topology since the first and the third mode current loopsare nearly opposite in direction and the field will be cancelledout In this circuit there is tendency to avoid extra ldquoband-aidrdquo circuitry like snubbers to reduce line current distortionand losses )e proposed 2-pscB converter shows a goodperformance suitable for high-frequency dcdc applicationswith high step-down ratios such as those in EV dc powerconverters and laptop power suppliers )ese applicationsare restricted by physical size heat dissipation and inductorvariations
9 Summary
A new theoretical approach to design an automatic currentsharing scheme was presented for a 2-phase series-capacitorsynchronous buck converter )e effects of its phase un-balance and parasitic circuit elements were discussed An I2current feedback controller was used to regulate the outputvoltage as well as to balance the two-phase inductor currents
Experimental results were presented for an 110V12V6A 250 kHz 2-pscB converter with a newmultiphase isolatedgate driver
Data Availability
)e simulation and experimintal data used to support thefindings of this study are available from the correspondingauthor upon request
Conflicts of Interest
)e authors declare that there are no conflicts of interestregarding the publication of this paper
EMI
Fly-back converter
Seriescapacitors
Figure 21 Prototype of the 110V12V6A 2-pscB converter
Efficiency_simulationEfficiency_measured
Dissip_simulation (W)Dissip_measured (W)
Pow
er lo
ss (W
)
Efficiency vs load current
0
01
02
03
04
05
06
07
08
09
1
Effic
ienc
y
1 2 3 4 5 60Load current (A)
0
1
2
3
4
5
6
7
8
Figure 22 Simulated and experimental efficiencies versus load currents
14 Journal of Electrical and Computer Engineering
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
References
[1] K Abe K Nishijima K Harada T Nakano T Nabeshimaand T Sato ldquoA novel three-phase buck converter withbootstrap driver circuitrdquo in Proceedings of the IEEE PowerElectronics Specialists Conference Orlando FL USA June2007
[2] K Matsumoto K Nishijima T Sato and T Nabeshima ldquoAtwo-phase high step down coupled-inductor converter fornext generation low voltage CPUrdquo in Proceedings of the 8thInternational Conference on Power Electronics-ECCE AsiaJeju Korea June 2011
[3] B Oraw and R Ayyanar ldquoSmall signal modeling and controldesign for new extended duty ratio interleaved multiphasesynchronous buck converterrdquo in Proceedings of the INTELEC06-Twenty-Eighth International Telecommunications EnergyConference Providence RI USA September 2006
[4] M M Jovanovic D E Crow and L Lieu Fang-Yi ldquoA novellow-cost implementation of ldquodemocraticrdquo load-currentsharing of paralleled converter modulesrdquo IEEE Transactionson Power Electronics vol 11 no 4 pp 604ndash611 1996
[5] D J Perreault R L Selders and J G Kassakian ldquoFrequency-based current-sharing techniques for paralleled power con-vertersrdquo IEEE Transactions on Power Electronics vol 13 no 4pp 626ndash634 1998
[6] L Hua and S G Luo ldquoDesign considerations for small signalmodeling of dc-dc converters using inductor DCR currentsensing under time constants mismatch conditionsrdquo inProceedings of the IEEE Power Electronics SpecialistsConference Orlando FL USA June 2007
[7] S Mazumder M Tahir and K Acharya ldquoMasterndashslavecurrent-sharing control of a parallel DC-DC converter systemover an RF communication interfacerdquo IEEE Transactions onIndustrial Electronics vol 55 no 1 pp 59ndash66 2008
[8] P Midya P T Krein and M F Greuel ldquoSensorless currentmode control-an observer-based technique for DC-DCconvertersrdquo IEEE Transactions on Power Electronics vol 16no 4 pp 522ndash526 2001
[9] K Nishijima K Harada T Nakano T Nabeshima andT Sato ldquoAnalysis of double step-down two-phase buckconverter for VRMrdquo in Proceedings of the INTELEC 05-Twenty-Seventh International TelecommunicationsConference Berlin Germany September 2005
[10] J A A Qahouq and L Huang ldquoHighly efficient VRM for wideload range with dynamic non-uniform current sharingrdquo inProceedings of the APEC 07-Twenty-Second Annual IEEEApplied Power Electronics Conference and Exposition Ana-heim CA USA March 2007
[11] P Shenoy M Amaro J Morroni and D Freeman ldquoCom-parison of a buck converter and a series capacitor buckconverter for high-frequency high-conversion-ratio voltageregulatorsrdquo IEEE Transactions on Power Electronics vol 31no 10 2016
[12] P S Shenoy M Amaro D Freeman and J MorronildquoComparison of a 12V 10A 3MHz buck converter and aseries capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Charlotte NC USA March 2015
[13] Z Lukic Z Zhao A Prodic and D Goder ldquoDigital controllerfor multi-phase dcdc converters with logarithmic currentsharingrdquo in Proceedings of the IEEE Power Electronics Spe-cialists Conference Orlando FL USA June 2007
[14] Texas Instruments TI Datasheet TPS54A20 8-V to 14-VInput 10-A up to 10-MHz SWIFTtrade Step Down Converter2016 httpwwwticomlitdssymlinktps54a20pdf
[15] P Shenoy O Lazaro R Ramani M Amaro and W WiktorldquoA 5MHz 12V 10A monolithically integrated two-phaseseries-capacitor buck converterrdquo in Proceedings of the IEEEApplied Power Electronics Conference and Exposition (APEC)Long Beach CA USA March 2016
[16] P Shenoy O Lazaro and M Amaro ldquoAutomatic currentsharing mechanism in the series capacitor buck converterrdquo inIEEE Energy Conversion Congress and Exposition (ECCE)Detroit MI USA September 2015
[17] P Shenoy andM Amaro ldquoImproving light load efficiency in aseries capacitor buck converter by uneven phase interleavingrdquoin Proceedings of the IEEE Applied Power Electronics Con-ference and Exposition (APEC) Charlotte NC USA March2015
[18] Texas Instruments ldquoTI datasheet single gate driverldquoUCC2753xrdquordquo 2012 httpwwwticomproductUCC27531
[19] X Zhou P Xu and F C Lee ldquoA novel current-sharingcontrol technique for low-voltage high-current voltage reg-ulator module applicationsrdquo IEEE Transactions on PowerElectronics vol 15 no 6 pp 1153ndash1162 2000
[20] G Zhou J Xu and J Wang ldquoConstant-frequency peak-ripple-based control of buck converter in CCM reviewunification and dualityrdquo IEEE Transactions on IndustrialElectronics vol 61 no 3 pp 1280ndash1291 2014
[21] S Maniktala Simple Switcherreg PCB Layout Guidelines Na-tional Semiconductor Dallas TX USA
[22] AN-1229 Simple Switcherreg PCB Layout Guidelines httpwwwticomlitansnva054csnva054cpdf
[23] Infineon Datasheet N-OptiMOSTM3 power-transistorMOSFETs IPD530N15N3 2013
Journal of Electrical and Computer Engineering 15
Recommended