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IBM SRDC
FINFET on SOI FINFET on SOI
Terence HookIBM SRDC
FDSOI Workshop, San Francisco, California, 2012
Feb 24, 2012
IBM Semiconductor Research and Development Center
OutlineOutline
FinFet and FDSOI Similarities
ElectrostaticsAccess resistance Threshold fluctuations
DifferencesPhysical OrientationDensityBackgate effect
Finfet on SOI substrates Process sequence Structural results Similarities and Differences with PDSOI planar
Finfet on bulk Similarities and differences with bulk planar Effects of doping
Feb 24, 2012
IBM Semiconductor Research and Development Center
A decade of A decade of FinfetsFinfets at IBM at IBM a representative surveya representative survey
D. Fried DRC
10nm50nm
T. Yamashita, VLSI
J. Chang VLSILooking ahead to 4nm!
V. Basker, VLSI
H. Kawasaki IEDM
K.Maitra EDL
J. Kedzierski IEDM
E.Nowak IEDM
T. Yamashita VLSI
E.Nowak CICC
P. Oldiges EDL.
2002
2003
2009
2010
2011
2001
Feb 24, 2012
IBM Semiconductor Research and Development Center
FINFET (FINFET (ieie, DG) electrostatics, DG) electrostatics
Gate
S D
= tdep +si/oxtoxL ~ 1/N
= 2(tsi +si/oxtox)Lmin ~ 3tsi+9tox
= tsi +si/ox2toxLmin ~ 1.5tsi+9tox
/2
Scaling requires increased doping loss, GIDL, high Cj, RDF
D. Frank, et al.2004 IEEE SOI Short CourseHuang & Nowak
Finfet device of same minimum channel length has ~twice the body thickness of FDSOI device
GateSubstrate
Gate Gate
DSDS
BOX
Feb 24, 2012
IBM Semiconductor Research and Development Center
0
50
100
150
200
15 20 25 30 35 40 45
Lgate
D
I
B
L
@
0
.
9
V
Short channel effects controlled by geometry of device
Use of fully-depleted (FD) device helps obtain DIBL
Feb 24, 2012
IBM Semiconductor Research and Development Center
Superior Superior VddVdd Scalability of AC PerformanceScalability of AC Performance
PDSOI
SOI FINFET
Superior Vdd scalability of RO AC performance in FINFET due to much improved electrostatics.
Feb 24, 2012
IBM Semiconductor Research and Development Center
PDSOI PDSOI FDSOI FDSOI FinfetFinfet
Curre
nt
flowFin
Gate
Source
Drain
FinFET
Gate
Source
Current flow
Drain
Gate
Source
Current flow
Drain
PDSOI
Gate
Source
Current flow
Drain
FDSOI
Gate
Source
Current flow
Drain
FDS
OI
Gate
Source
Current flow
Drain
Feb 24, 2012
IBM Semiconductor Research and Development Center
FINFET FINFET CrossCross--sectionssections
Cross-section parallel to fin Cross-section perpendicular to fin
Fin
Gate
current flow
source
drain
Tfin = 40nmW contact
Lgate = 140nm
BOXBOX
Feb 24, 2012
IBM Semiconductor Research and Development Center
Mobility on surfaceMobility on surface
Channel is formed on surface when fins are formed from (100) substrate
PFET mobility improves significantly ~2x improvement as expected Measurements show NFET mobility not degraded
significantly NFET degradation is
Feb 24, 2012
IBM Semiconductor Research and Development Center
Electrical vs. Physical FET WidthElectrical vs. Physical FET Width-- FinFin--Effect Effect --
FinFETs are like The Tardis Electrical WEFF ~ 1.5 x WPhysical possible. FET Specifications quoted per WEFF Physical Densities can be up to 1.5X higher (C and I)
80nm
WEFF= 2 x (25nm + 10nm + 25nm) = 120nm
WPY=80nm
25nm
10nm
Foot
Wafe
r
Chan
nel c
urren
t
(gate not shown)
Representative calculation of reasonable dimensions
Feb 24, 2012
IBM Semiconductor Research and Development Center
Access resistanceAccess resistance
Both thin-body devices use epitaxy to dope and fatten the body beyond the gate
Modern bulk and SOI use epitaxial source/drains also
FDSOI Finfet
Feb 24, 2012
IBM Semiconductor Research and Development Center
Current flow from fin into contact is 3Current flow from fin into contact is 3--dimensionaldimensional
With the gate removed the active fins may be seen
S
D
G
Feb 24, 2012
IBM Semiconductor Research and Development Center
EpitaxyEpitaxy engineering engineering
Engineering the connection to the thin body is the subject of much work in both FDSOI and Finfet
Yamashita et al, ECS 2011
Merged epitaxy
Unmerged epitaxy
Feb 24, 2012
IBM Semiconductor Research and Development Center
Threshold FluctuationsThreshold Fluctuations
In the ideal case the bodies of both FDSOI and Finfet are undoped, which eliminates random dopant fluctuation as a component of threshold variation
Endo et al., IEDM 2011
Liu et al., VLSI 2010
Hook et al., IEDM 2011
Feb 24, 2012
IBM Semiconductor Research and Development Center
Substrate effectSubstrate effect
In FDSOI there are two (maybe 1 and ?) gates and the threshold voltage may be modulated (dynamically if desired) by the potential on the back gate
This is similar, but superior, to the bulk fet case In Finfet the substrate bias has little effect on the device
This is similar to the PDSOI case but for a different reasonIn PDSOI the substrate is shielded from the device by body dopingIn Finfet only a small portion of the device is exposed to the substrate potential
Backgate
Hook et al., SOI 2011
Feb 24, 2012
IBM Semiconductor Research and Development Center
FinFETOn SOI
ConventionalSOI
SOI starting wafer
Nitride/oxide Films,Etch silicon islandsOxide isolation planarization.
Nitride/oxide Films,Etch silicon fins
and source/drain regions.
Simplified Process:
Si3N4/SiO2
silicon
Trench Fill (SiO2)
silicon
Conventional SOI, Only:Shallow Trench Sequence:Oxidize sidewallDep SiO2PlaraizeStrip pad films.
Feb 24, 2012
IBM Semiconductor Research and Development CenterProcess Flow 2Process Flow 2
Conventional SOI
- Gate deposition (dummy gate), planarization, pattern & etch.- Spacers- Ion-Implant extensions and halos (optional in FinFET)
spacers
Gate
FinFET SOI
Feb 24, 2012
IBM Semiconductor Research and Development CenterProcess Flow 3Process Flow 3
Conventional SOI
-Merge Fins (Grows epi Si/SiGe/SiC)-Insitu-doped or I/I
FinFET SOISelective Epitaxial Growth
-Etch S/D silicon regions-Grow S/D epi (strain regions)-Insitu-doped or I/I
Feb 24, 2012
IBM Semiconductor Research and Development CenterProcess Flow 4Process Flow 4
Conventional SOIFinFET SOI
-Replacement Gate Sequence-Flow same in planar and Fin
Remove dummy gate, replace w/ metal
Feb 24, 2012
IBM Semiconductor Research and Development CenterProcess Flow 5Process Flow 5
Conventional SOIFinFET SOI
-MOL Sequence-Flow same in planar and Fin
-Vias, Silicide-Contacts to S/D-Contacts to gate (not illustrated)
Feb 24, 2012
IBM Semiconductor Research and Development Center
FinfetFinfet formation on SOIformation on SOIFin height is silicon thickness
Inter- and intra-device isolation is accomplished by removing unwanted fins
Feb 24, 2012
IBM Semiconductor Research and Development Center
FIN Uniformity is Critical for SCE/Variability ControlFIN Uniformity is Critical for SCE/Variability Control
Edge FIN profile is important; the challenge can be addressed by Cut-last(cut unwanted FIN post FIN definition).
(a)
(b)
0
50
100
150
200
0 5 10 15 20 25 30 35
Fin numberD
I
B
L
(
m
V
)
Conventional SIT process
New SIT process
NFET Lgate=25nmProcess A
Process B
Process A
Process B
T. Yamashita, IBM, VLSI 2011
Feb 24, 2012
IBM Semiconductor Research and Development Center
Fins and PDSOIFins and PDSOI
Like PDSOI: No isolation wells
No latchup concerns
Low source/drain parasitic capacitance
Floating-node antenna design rules apply
Unlike PDSOI: No history effect
No body contacted devices possible (or needed!)
Device width is quantized
Feb 24, 2012
IBM Semiconductor Research and Development Center
SOI FINFET vs. Bulk FINFETSOI FINFET vs. Bulk FINFET
Active fin height set by oxide thickness and etched fin height
Active fin height set by SOI thickness
Bottom portion (at least) of the fin needs to be doped
Feb 24, 2012
IBM Semiconductor Research and Development Center
PunchthroughPunchthrough, or bulk, or bulk--fetfet regionregion
There must be enough doping to prevent this region from dominating the off-state conduction
Feb 24, 2012
IBM Semiconductor Research and Development Center
Suppressing SubSuppressing Sub--Fin Leakage in Bulk Fin Leakage in Bulk MuGFETsMuGFETs
(1) (2) (3)
1) In a perfect world.
2) Reduce RSD height relative to Hfin (deltaHsd) gate extends below S/D permits fin/substrate doping reduction, but requires same Hfin as #1.
3) Reduce Hfin and extend gate into local trench (deltaHg) to recover Wchannel from Hfin reduction similar effect as #2.
In real world, we can pull back source/drain depth and pull-down PC to overcome device variability - this can impose a performance hit (both R and C penalty).
1E-11
1E-10
1E-9
1E+17 1E+18 1E+19Doping (cm-3)
I
m
i
n
/
W
e
f
f
(
A
/
u
m
)
W10H30, deltaHsd=0W13H24, deltaHsd=0W10H30, deltaHsd=10W13H24, deltaHsd=10
Reduced sub-fin thermal leakage
BTBT
Ideal case s/d Pull Back Additional PC pull-down
R. Vega, IBM
Feb 24, 2012
IBM Semiconductor Research and Development Center
FIN Doping FIN Doping Some Boundary ConditionSome Boundary Condition
Similar to planar device, channel doping is an effective knob for Vt tuning (and multiVt solution).
Due to the constraint on Vtmm and AVT, the maximum doping allowed in channel is ~1-2E18/cm3.
C.H. Lin, IBM
Feb 24, 2012
IBM Semiconductor Research and Development Center
FIN Doping FIN Doping Impact on MobilityImpact on Mobility
0.0 0.5 1.0 1.5 2.0 2.5
0
50
100
150
200M
o
b
5
Eeff5 (MV/cm)
1015
1017
1018
High Field = 1MV/cm of Inversion charge
Esimate of 6e18 Mo
b
i
l
i
t
y
,
a
r
b
u
n
i
t
s
Eeff
Edge, Linder, IBM
Scaling BULK and PDSOI SCE beyond 32nm requires body doping in excess of 5e18/cm3 - Mobility significantly degraded.
Undoped or Lightly doped FIN helps carrier mobility in addition, device is parked at lower vertical field at fixed Vdd, additional boost in mobility.
Feb 24, 2012
IBM Semiconductor Research and Development Center
Fins and bulk planarFins and bulk planar Like bulk planar:
Use conventional nfet/pfet isolation wells Conventional latchup tap rules Conventional bulk antenna design rules apply
Unlike bulk planar: No body contacted devices possible (or needed!) Device width is quantized Negligible body effect
Something like bulk planar: Subsurface drain-source punchthrough suppression Junction area capacitance
Feb 24, 2012
IBM Semiconductor Research and Development Center
FinfetsFinfets on SOIon SOI Electrostatic benefits like FDSOI
Low voltage, high threshold operation Obviates need for tinv and Xj scaling
Low doping benefits like FDSOI High mobility Low RDF
Some challenges similar to FDSOI Epitaxial source/drain and access resistance
Some aspects entirely different than FDSOI 3D processing 3D density effect Width quantization
SOI is a convenience for Finfet while it is intrinsic to FDSOI Bulk finfet is a viable option
Feb 24, 2012
IBM Semiconductor Research and Development Center
AcknowledgementAcknowledgement
The talk is based on the work of, as well as discussions with:
H. BuE. NowakA. BryantJ. Johnson C.H. Lin M. FujiwaraJ. ChoR. MillerT. YamashitaR. VegaP. ZeitzoffV. BaskerT. Standaert
And many others in Albany, Burlington, and East Fishkill
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