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241-440 @ W.S.
241-440 Computer Syste
m Design Lecture 4
Wannarat Suntiamorntut
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Part I : Single D ata Path
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Outline Design a Processor step by step Requirement of instruction set Components and clocking Testing Datapath Control Datapath
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Five Componen t of Computer
Datapath
Control
Processor
MEMORY
Input
Output
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Performance Perspective Performance of machine is determin
ed by CPI Processor Design :
clock cycle time clock per instruction
Single cycle processor : adv. : one clock cycle per instruction
disadv. : long cycle time
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Design Process or Step by Step
1. Analyze instruction set ==> Datapa th requirement
2. Selection Set of datapath and estab lish clocking methodology
3 . Assembly datapath meeting requirement 4.Analyze implementation of each instruct
i ontodetermi ne setti ngof control 5.Assembly the control logic
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MIPS Instructio n Format
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Step 1 AA A A rd,rs,rt SUBUrd,rs,rt
ORI rt, rs, imm1 6
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Step 1 16 16lw rt, rs ,imm sw rt, rs, imm
16beq rs, rt, imm
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AAA All instructions start by fetching
Mem[PC] ADDU rd <= rs + rt; PC = PC + 4
SUBU rd <= rs + rt; 4PC = PC +Ori rt <= rs + zero_ext(imm16);PC = PC + 4
16LOAD rt <= mem[rs] + sign_ext(imm ); PC=PC +4
STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4BEQ 16 00if rs = rt then PC=PC+sign_ext(imm )||
else PC = PC + 4
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1Step : The requirement froA AAAAAAAAAAA
Memory Data & Instruction
Register (32 x 32) Read rs AAAA AA AAAAA AA AA AA
PC AAAAAAAA AAA AAA AAA AAAAAAAA AA AAAAAA AAAAAAAAA Add 4 or extended immediate to PC
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Step 2 : Compon ents of datapath
Combination Element Storage elements
Clocking methodology
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Combination Elements
Adder MUX
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Combination Elements
ALU
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Storage Elemen t : Register
-Similar to D flip/flop A AAAA AAAAAA
AAAA AAA (0) : AAAAAA’
asserted(1 ) : Data out wi l l be data i n
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Register file 32Consist of registers
A A AAAAAA AAAAAAAA AA AAA A Rbsel ect regi ster tobus B Rw select register to be written via bus W
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Storage : IdealMemory One Input One Output Memory word is selected
by Address, Write enable = 1 then the data will be written
Clock input : is a factor only during write operation
During read operation : behaves on com bination logic.
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Clock Methodology
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Step 3 : Register Transfer Requirements
-- AAAAAAAA AAAAAAAA> Instruction Fetch Read Operands and Execute Operati
AA
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Step 3 a : Instruc tion Fetch Unit
Update PC : Sequence Code: PC <= PC + 4 - Branch and Jump : PC < something else
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Step 3b : Add &Sub
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-Register Regist er Timing
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3Step c :Logical Opera AAAA AAAAAA.
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Step 3d: Load operations
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Step 3e : StoreOperations
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Step 3f: Branchinstruction
AAA AA A AAA16
[ ] A AA<= = if (con eq 0 ) then PC<=PC+4 +(sig
nExt(imm16)x4); else PC <= PC + 4;
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Datapath for Br anch Operations
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Put it all together
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Abstract view of critical path
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Step 4 : ControlPath
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Meaning of cont rol signal
Rs, Rt and Imme16 hardwire to datapaAA
nPC_sel : 0 => PC PC<= PC+4, 1 => PC PC <= PC + 4 +
16 00signExt(Imm ) ||
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Meaning of cont rol signals
ExtOp : Zero, sign MemWr :write memoryALUsrc: 0=>regB, 1=>imme Memtoreg:1=>memALUcrt : add, sub, or
ReqWr : write dest. Reg.
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Control Signals
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5Step : Logic for eaAA AAAAAAA AAAAAA
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Example : LoadFlow
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Abstract View ofimplementation
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AA AAAAAAA A5
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