1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015

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COMP541

Arithmetic Circuits

Montek Singh

Oct 21, 2015

Today’s Topics Adder circuits

ripple-carry adder (revisited)more advanced: carry-lookahead adder

Subtractionby adding the negative

Overflow

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Iterative Circuit Like a hierarchy, except functional blocks per

bit

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Adders Great example of this type of design Design 1-bit circuit, then expand Let’s look at

Half adder – 2-bit adder, no carry in Inputs are bits to be addedOutputs: result and possible carry

Full adder – includes carry in, really a 3-bit adder

We have already studied adder in Lab 3/Comp411here we look at it from a different anglemodify it to be faster

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Half Adder Produces carry out

does not handle carry in

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Full Adder Three inputs

third is carry in Two outputs

sum and carry out

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Two Half Adders (and an OR)

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Ripple-Carry Adder

Straightforward – connect full adders Carry-out to carry-in chain

Cin in case this is part of larger chain, or just ‘0’

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32-bit ripple-carry adder

Lab 3: Hierarchical 4-Bit Adder We used hierarchy in Lab 3

Design full adderUsed 4 of them to make a 4-bit adderUsed two 4-bit adders to make an 8-bit adder…

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Specifying Addition in Behavioral Verilog// 4-bit Adder: Behavioral Verilog

module adder_4_behav(A, B, C0, S, C4);input wire[3:0] A, B;input wire C0;output logic[3:0] S;output logic C4;

assign {C4, S} = A + B + C0;endmodule

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Addition (unsigned)

Concatenation operation

What’s the problem with this design?

DelayApprox how much?

Imagine a 64-bit adderLook at carry chain

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Delays (after assigning delays to gates)

Delays are generally higher for more significant bits

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Multibit Adders Several types of carry propagate adders (CPAs)

are:Ripple-carry adders (slow)Carry-lookahead adders (fast)Prefix adders (faster)

Carry-lookahead and prefix adders are faster for large adders but require more hardware.

Adder symbol (right)

A B

S

Cout Cin+N

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Carry Lookahead Adder Note that add itself just 2 level

sum is produced with a delay of only two XOR gatescarry takes three gates, though

Idea is to separate carry from adder function then make carry fasteractually, we will make carry have a 2-gate delay total,

for all the bits of the adder!these two gates might be huge though

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Four-bit Ripple Carry

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Adder functionseparated fromcarry

Notice adder has A, B, C inand S out, as well as G,P out.

Reference

Propagate The P signal is called propagate

P = A B Means to propagate incoming carry

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Generate The G is generate

G = AB, so new carry created So it’s ORed with incoming carry

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Said Differently If A B and there’s incoming carry, carry will

be propagatedAnd S will be 0, of course

If AB, then will create carry Incoming will determine whether S is 0 or 1

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Ripple Carry Delay: 8 Gates Key observation:

G and P are produced by each adder stagewithout needing carry from the right!

need only 2 gate delays for all G’s and P’s to be generated!critical path is the carry logic at the bottom

the G’s and P’s are “off the critical path”

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Turn Into Two Gate Delays Refactor the logic

changed from deep (in delay) to widefor each stage, gather and squish together all the logic to

the right

C1 Just Like Ripple Carry

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C2 Circuit Two Levels

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G from before and P to pass on This checks two propagates and a carry in

C3 Circuit Two Levels

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G from before and P to pass onThis checks three propagates and a carry in

Generate from level 0 and two propagates

What happens as scaled up? Can I realistically make 64-bit adder like this? Have to AND 63 propagates and Cin! Compromise

Hierarchical designMore levels of gates

use a tree of AND’sdelay grows only logarithmically

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Making 4-Bit Adder Module

Create propagate and generate signals for whole module

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Group Propagate

Make propagate of whole 4-bit block P0-3 = P3P2P1P0

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Group Generate

Indicates carry generated within this block

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Hierarchical Carry

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4-bit adder

A B

S G P Cin

4-bit adder

A B

S G P Cin

C0Look Ahead

C8 C4

Left lookahead block is exercise for you

Practical Matters FPGAs like ours have limited inputs per gate

Instead they have special circuits to make addersSo don’t expect to see same results as theory would

suggest

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Other Adder Circuits What if hierarchical lookahead too slow Other styles exist

Prefix adder (explained in text) had a tree to computer generate and propagate

Pipelined arithmetic units – multicycle but enable faster clock speed

These are for self-study

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Adder-Subtractor Need only adder and complementer for input

to subtract

Need selective complementer to make negative output back from 2’s complement

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Design of Adder/Subtractor

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Output is 2’s complement if B > A

Inverts each bit of B if S is 1

Adds 1 to make 2’s complement

S low for add,high for subtract

Overflow Two cases of overflow for addition of signed

numbersTwo large positive numbers overflow into sign bit

Not enough room for resultTwo large negative numbers added

Same – not enough bits

Carry out by itself doesn’t indicate overflow

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Overflow Examples4-bit signed numbers:

Sometimes a leftmost carry is generated without overflow: -7 + 75 + (-3)

Sometimes a leftmost carry is not generated, but overflow occurs:4 + 4

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Overflow Detection Basic condition:

if two +ve numbers are added and sum is –ve if two -ve numbers are added and sum is +ve

Can be simplified to the following check:either Cn-1 or Cn is high, but not both

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Summary Today

adders and subtractorsoverflow

Next class: full processor datapath

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