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COMP541COMP541

Sequential CircuitsSequential Circuits

Montek SinghMontek Singh

Feb 1, 2012Feb 1, 2012

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TopicsTopics Sequential CircuitsSequential Circuits

LatchesLatches Flip FlopsFlip Flops

Verilog for sequential designVerilog for sequential design Example: A simple counterExample: A simple counter

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Sequential CircuitsSequential Circuits StateState of system is info stored of system is info stored That, and inputs, determine outputsThat, and inputs, determine outputs

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Types of Sequential CircuitsTypes of Sequential Circuits SynchronousSynchronous

State changes synchronized by one or more clocksState changes synchronized by one or more clocks

AsynchronousAsynchronous Timing of changes are independent of any clocksTiming of changes are independent of any clocks

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Clocking of SynchronousClocking of Synchronous Changes enabled by clockChanges enabled by clock

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ComparisonComparison SynchronousSynchronous

Easier to analyze because can factor out gate delaysEasier to analyze because can factor out gate delays Set clock so changes occur before next clock pulseSet clock so changes occur before next clock pulse

AsynchronousAsynchronous Potentially fasterPotentially faster Harder to analyze (more subtle, but more powerful!)Harder to analyze (more subtle, but more powerful!)

Most of my research!Most of my research!

Will look mostly at synchronousWill look mostly at synchronous

Storage ElementsStorage Elements LatchLatch Flip-Flop – a latch that transitions on a clockFlip-Flop – a latch that transitions on a clock RegistersRegisters Addressable memories or banks of registersAddressable memories or banks of registers

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Basic StorageBasic Storage Apply low or high for longer than tApply low or high for longer than tpdpd

Feedback will hold valueFeedback will hold value

Bistable Circuit AnalysisBistable Circuit Analysis Consider 2 possible Consider 2 possible

cases:cases: Q = 0: then Q’ = 1 and Q Q = 0: then Q’ = 1 and Q

= 0 (consistent)= 0 (consistent)

Q = 1: then Q’ = 0 and Q Q = 1: then Q’ = 0 and Q = 1 (consistent)= 1 (consistent)

Bistable circuit stores 1 Bistable circuit stores 1 bit of state in the state bit of state in the state variable, Q (or Q’)variable, Q (or Q’)

But there are no inputs But there are no inputs to control the stateto control the state

Q

Q

I1

I2

0

1

1

0

Q

Q

I1

I2

1

0

0

1

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SR (set-reset) LatchesSR (set-reset) Latches Basic storage made from gatesBasic storage made from gates

•S & R both 0 in “resting” state•Have to keep both from 1 at same time

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OperationOperation

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LatchLatch Similar – made from NANDsSimilar – made from NANDs

RS

SR Latch SummarySR Latch Summary SR stands for Set/Reset LatchSR stands for Set/Reset Latch

Stores one bit of state (Q)Stores one bit of state (Q)

Control what value is being stored with S, R Control what value is being stored with S, R inputsinputs Set: Make the output 1 (S = 1, R = 0, Q = 1)Set: Make the output 1 (S = 1, R = 0, Q = 1) Reset: Make the output 0 (S = 0, R = 1, Q = 0)Reset: Make the output 0 (S = 0, R = 1, Q = 0)

Behavior undefined/invalid when:Behavior undefined/invalid when: S = R = 1S = R = 1

S

R Q

Q

SR LatchSymbol

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Add Control InputAdd Control Input Gates when state can changeGates when state can change

Is there latch w/ no illegal state?Is there latch w/ no illegal state?

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D-type LatchD-type Latch No illegal stateNo illegal state

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Transparency of latchesTransparency of latches As long as C (the As long as C (the control control )) isis high, state can high, state can

changechange This is called This is called transparencytransparency

What’s problem with that?What’s problem with that?

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Effects of TransparencyEffects of Transparency Output of latch may feed backOutput of latch may feed back

May cause/allow further state changesMay cause/allow further state changes Behavior depends on actual gate delaysBehavior depends on actual gate delays

Want to change latch state only Want to change latch state only onceonce Behavior should depend only on logical valuesBehavior should depend only on logical values

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Solution to Transparency: Flip-Solution to Transparency: Flip-FlopsFlops Flip-Flops:Flip-Flops:

Ensure output changes only once per clock cycleEnsure output changes only once per clock cycle

Two commonly-used types of flip-flops:Two commonly-used types of flip-flops: Master-SlaveMaster-Slave

Use a sequence of two latchesUse a sequence of two latches Edge-TriggeredEdge-Triggered

Implementation very different from latchesImplementation very different from latches

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1. Master-Slave Flip-Flop1. Master-Slave Flip-Flop Either Master or Slave is enabled, not bothEither Master or Slave is enabled, not both

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Timing DiagramTiming Diagram

Trace the behaviorTrace the behavior Note illegal stateNote illegal state Is it transparent?Is it transparent?

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Have We Fixed the Problem?Have We Fixed the Problem? Output no longer transparentOutput no longer transparent

Combinational circuit can use last valuesCombinational circuit can use last values New inputs appear at latchesNew inputs appear at latches Not sent to output until clock lowNot sent to output until clock low

But changes at input of FF when clock high do But changes at input of FF when clock high do trigger next statetrigger next state Is this a problem?Is this a problem?

As clock faster, more problemsAs clock faster, more problemsHave to guarantee circuit settles while clock lowHave to guarantee circuit settles while clock low

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2. Edge-Triggered Flip-Flops2. Edge-Triggered Flip-Flops New state latched on New state latched on clock transitionclock transition

Low-to-high or high-to-lowLow-to-high or high-to-low+ve edge-triggered, -ve edge-triggered+ve edge-triggered, -ve edge-triggeredAlso: dual-edge-triggeredAlso: dual-edge-triggered

Changes when clock high are ignoredChanges when clock high are ignored

Note: Master-Slave sometimes called Note: Master-Slave sometimes called pulse pulse triggeredtriggered

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D-Type Edge-TriggeredD-Type Edge-Triggered

Is this +ve or –ve edge-triggered?Is this +ve or –ve edge-triggered?

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Standard Symbols – LatchesStandard Symbols – Latches

Circle at input indicates negationCircle at input indicates negation

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Symbols – Master-SlaveSymbols – Master-Slave Inverted Inverted ‘‘LL ’’ indicates postponed output indicates postponed output Circle indicates whether enable is positive or Circle indicates whether enable is positive or

negativenegative

JK: like an SR flip-flop, but:JK: like an SR flip-flop, but: If J=K=1, output is toggledIf J=K=1, output is toggled Can make a toggle flip-flop (T flip-flop) from a JKCan make a toggle flip-flop (T flip-flop) from a JK

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Symbols – Edge-TriggeredSymbols – Edge-Triggered

Arrow indicates edge triggerArrow indicates edge trigger

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Direct InputsDirect Inputs Use to force Set/Reset independent of clockUse to force Set/Reset independent of clock

Direct set or Direct set or presetpreset Direct reset or Direct reset or clearclear

Often used for power-up resetOften used for power-up reset

RegistersRegisters

CLK

D Q

D Q

D Q

D Q

D0

D1

D2

D3

Q0

Q1

Q2

Q3

D3:0

4 4

CLK

Q3:0

CountersCounters Increments on each clock Increments on each clock

edgeedge Used to cycle through Used to cycle through

numbers For example, numbers For example, 000, 001, 010, 011, 100, 101, 000, 001, 010, 011, 100, 101,

110, 111, 000, 001…110, 111, 000, 001… Not necessarily binaryNot necessarily binary

Example uses:Example uses: Digital clock displaysDigital clock displays Program counterProgram counter

Q

CLK

ResetN

+

N

1

CLK

Reset

N

NQN

r

Symbol Implementation

Verilog for SequentialVerilog for Sequential New Verilog to describe sequential circuitsNew Verilog to describe sequential circuits

Can use latches and flip-flops from library in Can use latches and flip-flops from library in schematic capture or Verilogschematic capture or Verilog

And connect them using wiresAnd connect them using wires

But more productive to write higher-level But more productive to write higher-level Verilog descriptionVerilog description

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Register Data TypeRegister Data Type Like Like wirewire but value is retained over time but value is retained over time Often causes latch or FF to be synthesizedOften causes latch or FF to be synthesized ExamplesExamples

reg state;reg state;

reg [15:0] addr;reg [15:0] addr;

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Always BlockAlways Block ExampleExample

always @ ( always @ ( sensitivity list sensitivity list ))

statementstatement;;

Sensitivity list determines what might affect Sensitivity list determines what might affect statementsstatements Could think of it as “Could think of it as “statementstatement is run when one of is run when one of

values in sensitivity list changes value”values in sensitivity list changes value”

Example nextExample next

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Synthesize a Flip-FlopSynthesize a Flip-Flopmodule flop (C, D, Q); module flop (C, D, Q);     input C, D; input C, D;     output Q; output Q;

    reg Q; reg Q;

    always @(posedge C) always @(posedge C)         begin begin             Q = D; Q = D;         end end endmodule endmodule

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negedge also possible

Blocking AssignmentBlocking Assignment Equal sign indicates Equal sign indicates blockingblocking statements statements

initialinitialbeginbegin

B = A;B = A;C = B;C = B;

endend Result is that Result is that newnew contents of B are in C, so all contents of B are in C, so all

have contents of A.have contents of A.

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Non-Blocking AssignmentNon-Blocking Assignment <= indicates <= indicates non-blockingnon-blocking statements statements

initialinitial

beginbegin

B <= A;B <= A;

C <= B;C <= B;

endend

All RHS evaluated first, then assignedAll RHS evaluated first, then assigned Result is that Result is that old old contents of B are in Ccontents of B are in C This is what is normally synthesized!!!This is what is normally synthesized!!!

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This is Not Software!This is Not Software! Don’t assign to same reg in more than one Don’t assign to same reg in more than one

always blockalways block The always blocks are concurrentThe always blocks are concurrent DoesnDoesn’’t make sense to set reg from two signalst make sense to set reg from two signals

Assignments in always blocks should be non-Assignments in always blocks should be non-blockingblocking You usually donYou usually don’’t mean sequential executiont mean sequential execution CanCan’’t synthesize anyway!t synthesize anyway!

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Asynchronous ResetAsynchronous Resetmodule dff_v(CLK, RESET, D, Q);module dff_v(CLK, RESET, D, Q); input CLK, RESET, D;input CLK, RESET, D; output Q;output Q;

reg Q;reg Q;

always @(posedge CLK or posedge RESET)always @(posedge CLK or posedge RESET) beginbegin if (RESET)if (RESET)

Q <= 0;Q <= 0; elseelse Q <= D;Q <= D; endend endmodule endmodule

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Synchronous ResetSynchronous Resetalways @(posedge CLK)always @(posedge CLK) beginbegin if (RESET)if (RESET)

state <= 0;state <= 0; elseelse state <= D;state <= D; endend

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Verilog for a CounterVerilog for a Countermodule counter(input clk, output [23:0] cntmodule counter(input clk, output [23:0] cnt

););

reg [23:0] cnt;reg [23:0] cnt;

always @ (posedge clk)always @ (posedge clk)

cnt <= cnt + 1;cnt <= cnt + 1;

endmoduleendmodule

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Simulation vs SynthesisSimulation vs Synthesis If you don’t initialize regs in your circuits, If you don’t initialize regs in your circuits,

simulator will complainsimulator will complain many values will be Xmany values will be X

Electronics will work OKElectronics will work OK each reg in actual circuit will “wake up” to a 0 or 1 each reg in actual circuit will “wake up” to a 0 or 1

valuevalue

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Verilog 2001 SyntaxVerilog 2001 Syntax Can initialize regs at declarationCan initialize regs at declaration

reg onebit = 1reg onebit = 1’’b0; b0;

reg [3:0] fourbits = 4reg [3:0] fourbits = 4’’b1011;b1011;

reg [23:0] cnt = 0; reg [23:0] cnt = 0;

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TopicsTopics TodayToday

Looked at basic latchesLooked at basic latches Flip-flopsFlip-flops Verilog for sequential circuitsVerilog for sequential circuits Simple counterSimple counter

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ReadRead Textbook Ch. 3.1-3.3 for todayTextbook Ch. 3.1-3.3 for today

Ch. 3.4-3.5 for next classCh. 3.4-3.5 for next class

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Next TimeNext Time State MachinesState Machines

Verilog to describe Verilog to describe state machinesstate machines

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