Seminar 12-11-19

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Presentation Slides by Pipat Methavanitpong about the author for Seminar class Nov 19, 2012 at Kunieda-Isshiki Laboratory, Tokyo Institute of Technology.

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Pipat Methavanitpong (M1)

November 19, 2012

OUTLINE

Me

Fractional-order Sinusoidal Oscillator

Faster Microprocessors

Name: Pipat Methavanitpong

Nationality: Thailand

Graduated from: SIIT, Thammasat

University in 2012

Electronic and Communication

Engineering

Senior Project – Fractional-order

Sinusoidal Oscillator

Work Experience: none

Internship Experience: YES!!

NECTEC Integrated Circuit

Development Section Basic SystemC Syntax

Silicon Craft

Basic SRAM Schematic

Skills: have experienced many

programming languages both H/L level

[Experience does not mean

proficiency]

MATLAB, SIMULINK, OrCAD,

LabView

68HC11, 8086, Arduino, PLC

C, C#, Java, Groovy, SQL, HTML,

CSS, PHP, VHDL, Flex

Goal: Develop faster CPU than others in

the market

My Current Work: Support Surachai-san

developing Dalvik extension to Lab’s

TCT processor

ME <=

FRACTIONAL-ORDER SINUSOIDAL OSCILLATOR

Simple

MATH:

What I did

Follow Elwakil’s work

he provides generalization of design of n-

fractional-order devices oscillator

The only HOPE for my graduation!!

Literature review on Fractional-order

devices

Implement this knowledge in my advisor’s

Current Tunable Sinusoidal Oscillator ’87

Result – It works and oscillates faster

BUT, still have not fully understood what

fractional-order calculus is

Very complex calculation

FRACTIONAL-ORDER SINUSOIDAL OSCILLATOR

S. Pookaiyaudom, B. Srisuchinwong, and W. Kurutach,

“A Current-Tunable Sinusoidal Oscillator”, IEEE

Transactions on Instrumentation and Measurement, Vol.

IM-36, No. 3, September, pp. 725-729, Sep 1987.

WHY none in market

Creation of these devices is

NOT FEASIBLE

Realization from a mesh of

recursive R and C structure

Require LARGE area to

make it near ideal

performance

FRACTIONAL-ORDER SINUSOIDAL OSCILLATOR

5-level stage becomes this

mess

FRACTIONAL-ORDER SINUSOIDAL OSCILLATOR

1 level (LPF)

8 levels

12 levels

More levels -> More bandwidth

FRACTIONAL-ORDER SINUSOIDAL OSCILLATOR

HOPE, There is ! Such characteristic is found in organic things e.g.

There are reports of fabricated Si-devices for lab use.

An Advantage from this knowledge More precise control on every conventional circuits

Faster oscillator

Better PID controller

Any rate of attenuation electronic filter

Greener electronic devices

FASTER MICROPROCESSORS

How to become FASTER

YIN / YANG

An Era of Parallel Computing

Combination Dedicated Functionalities

Dark Silicon Gap

FASTER MICROPROCESSORS

How to become FASTER

2 choicesWork HARDER – Overclocking, Brute-force

Work SMARTER – Better algorithms and management

FASTER MICROPROCESSORS

YIN / YANG Everything has both advantages and disadvantages Analog systems No loss of data Very sensitive to interference

Digital systems Reconfigurable / Distortion Immunity Limited Range of Data (freq range)

Smaller MOSFET Faster / Lower power Higher power density / Undeterministic Quantum Mechanic Behavior

Single Electron Transistor Even lower power consumption Blurred digital state

It is we, the engineers, whose task is to push through the limitation and shift to new paradigm via BREAKTHROUGH

An Era of Parallel Computing We cannot keep clock frequency rising Power consumption / Heat

Move to the new paradigm Share works with friends

Teamwork is the key

Everybody may not be perfect

But, everybody can take part in a work to get it done

But, as we know in every group work we have faced as students, researchers, employees, and etc.

Unfair work distribution – Better Arbiter

Waterfall workflow – Better Dataflow

Communication problem - NoC

FASTER MICROPROCESSORS

The ANALOGY of modern

microprocessors is now same as

URBAN PLANNINGTransportation – Communication between modules

Company – Functionality

People - Data

Combination Dedicated FunctionalitiesOne does not fit all

Give a right job to a right person

AMD APU – A combination of CPU and GPU on a single chip

CPU – less core / more memory Control intensive

GPU – more core / less memory Computation intensive

CPU + FPGA – dynamic functionalities

FASTER MICROPROCESSORS

FASTER MICROPROCESSORS

Dark Silicon Gap A term by H. Esmaeilzadeh etal. – Dark Silicon and the End of

Multicore Scaling ’12

Underutiliztion of transistor integration capacity

As a number of cores keep rising, the efficiency of utilization from

parallelization becomes WORST