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Engineering
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs Nxfee: Buy your Projects on Online
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A High Throughput List Decoder Architecture for Polar Codes : Nxfee: Buy your Projects on Online
Education
BTech VLSI Projects
Engineering
Power Efficient Level Shifter for 16 nm FinFET near Threshold Circuits Nxfee: Buy your Projects on Online
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A High-Speed FPGA Implementation of an RSD-Based ECC Processor : Nxfee: Buy your Projects on Online
Engineering
EMDBAM: A Low-Power Dual Bit Associative Memory with Match Error and Mask Control Nxfee: Buy your Projects on Online
Engineering
Area-Aware Cache Update Trackers for Postsilicon Validation Nxfee: Buy your Projects on Online
Engineering
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs Nxfee: Buy your Projects on Online
Engineering
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers Nxfee: Buy your Projects on Online
Engineering
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures Nxfee: Buy your Projects on Online
Engineering
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits : Nxfee: Buy your Projects on Online
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Source Code Error Detection in High-Level Synthesis Functional Verification : Nxfee: Buy your Projects on Online
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Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication: Nxfee: Buy your Projects on Online
Engineering
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range Nxfee: Buy your Projects on Online
Engineering
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM : Nxfee: Buy your Projects on Online
Engineering
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation Nxfee: Buy your Projects on Online
Engineering
Code Compression for Embedded Systems Using Separated Dictionaries : Nxfee: Buy your Projects on Online
Engineering
RF Power Gating: A Low-Power Technique for Adaptive Radios : Nxfee: Buy your Projects on Online
Engineering
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation Nxfee: Buy your Projects on Online
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A New Binary-Halved Clustering Method and ERT Processor for ASSR System : Nxfee: Buy your Projects on Online
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