Slow dancing pdn on memory-controller-packages may-10th_2012_hf_last

‘SLOW-DANCING’

PDN FOR MEMORY

CONTROLLER

PACKAGES

May 10, 2012

Confidentiality Label

1

Hany M Fahmy

HSD Application Expert

Agilent Technologies Inc.

Davy Pissoort, KHBO-K.U. Leuven

May 10th , 2012

What is the Spectral Content of the SSO noise?

May 10, 2012


2

We have Strong Harmonics close to 10GHz for DDR3-1866

I am driving from the Voltage-Regulator to the

VddQ Die-Bumps, why I am having so many

accidents!!!!!

• Noise Frequency Distribution:

1. IR Drop (DC losses) through the whole path

2. VR noise in the KHz range (switching VR noise usually 450Khz to 500KHz for DDR3 systems) Controlled by the on-PCB decaps mainly

3. Low-Freq noise in the MHz range is controlled by the on-PCB decaps and also the on-PKG decaps do support as well

4. SSO noise in the GHz range is controlled by the on-die ad on-PKG decaps

MOM do provide a Single-Shot Solution from DC up to the GHz range of the SSO noise unlike conventional tools that do have separate solutions for IR-Drop then Low-Freq and Hybrid-Techniques can’t be used for SSO GHz noise

May 10, 2012


3

Proposed PDN Optimization Strategy:

- PDN Resonances & FD optimization of decaps MOM

+ ADS Schematic

- Co-SI/PI eye-sim Convolution Transient engine

- EMI & P2P FDTD Simulations with Icc(t) OR CPM

May 10, 2012


4

New Outlook at PI Problems in HSD systems

1. MOM-FD extraction of PDN for PKG & PCB

2. ADS-Schematic Lump on-die PDN model & VR & on-PKG decaps & on-PCB

decaps

3. ADS-Optimizer Optimize the PDN decaps for Target Impedance profile from

DC to the GHz range (detecting resonances & damp them using all decap

schemes on-die+on-PKG+on-PCB

4. MOM-FD Extraction of PDN+Data-nets for PCB & PKG (Example # 1)

5. ADS-Schematic lump on-die PD model & VR & on-PKG decaps & on-PCB

decaps obtained from # 3. Add VR low-frequency noise profile (switching VR

noise in the KHz range).

6. Transient Convolution TD analysis with IBIS model or BSIM4 models to study the

impact of VR-noise & SSO-noise & IR-drop all together on the data-eye-opening.

7. Measure the Current-profile Icc(t) on VddQ pins on PCB

8. FDTD of PCB Inject the current profile Icc(t) from # 7 to fine-tune the on-

PCB decaps for minimum Radiated-Emission of SSO noise (Example # 2)

May 10, 2012


5

EXAMPLE 1: STEPS # 1-3

DETECTION OF RESONANT

FREQUENCY OF THE WHOLE

PDN SYSTEM

OPTIMIZATION OF DECAPS TO

MEET CERTAIN IMPEDANCE

PROFILE

May 10, 2012


6

FD Optimization of the PDN network

May 10, 2012


7

Impact of decoupling schemes? FD Optimization

May 10, 2012


8

DIE

PKG

PCB

VR

EXAMPLE 2: STEP # 4

STUDYING THE RELATIONSHIP

BETWEEN RPD & NOISE-

COUPLING BETWEEN VDDQ &

DATA-NETS

May 10, 2012


9

Co-SI/PI Modeling OF Multi-Giga-bit EMI effects

10

• Signal layer transitions: L1-2-L3 is it same like L1-2-L5?

• Open-stubs of Vias

• Stitching vias impact (# & Locality)

Optimizing on-PKG

decaps for Minimum

coupling of Power-Noise

to Data-Signals

DDR3 Package Modeling using MOM DC to 20GHz

DQ nets major referencing to GND

May 10, 2012 11

Routing of DQ signals from Bumps-Top to Layer-3

running as Symmetric-SL sandwiched between

GND on Layers 2 & 4

May 10, 2012 12

DQ signals @ Die-Bumps DQ signals on Layer-3 as Symmetric-SL

Optimizing on-PKG

decaps for Minimum

Power-Noise to Signal-

Coupling

Moving from Layer-3 to Layer-6 through Signal-PTH

to pickup the Balls

May 10, 2012 13

DQ signals on Layer-3

DQ signals on Layer-6 routed

between GND on layers 5

Impact of GND-PTH stitching: Proximity & #

Original-Package: PKG1 with 15-GND-PTH

EMEA

2011

14


New Proposal-Package:PKG2 with ONLY 3-GND-

PTH

May 10, 2012 15


Test-case Package: PKG3 with 0-GND-PTH

May 10, 2012 16

FD Risk Assessment of VddQ-Noise coupling to

Data-Signals

May 10, 2012


17

ON-PKG DECAPS

PACKAGE MOM S-MODEL

PORTS DIE-BUMP & DECAPS & BALLS

& 8-DATA SIGNALS + DQS/DQS# + DQM

AC NOISE-SOURCE

SWEEPING

AMPLITUDE @ VDDQ-

BUMP

MB LOADING

MODEL

NOISE-COUPLING TO TOGGELLING DATA-SIGNALS

0V noise @ VddQ-Bump Cpkg

May 10, 2012


18

15 GND-PTH

DO ON-PKG DECAPS IMPACT

THE COUPLING-FREQ AND

AMOUNT OF COUPLING?

May 10, 2012


19


300mV noise @ VddQ-Bump

Cdie 50pF per I/O

Cpkg is 4.7uF

May 10, 2012


20

15 GND-PTH

100mV noise

coupling at

2.57GHz



Cdie 50pF per I/O

Cpkg is 0.001uF

May 10, 2012


21

15 GND-PTH

100mV noise

coupling at

2.57GHz &

180MHz



Cdie 50pF per I/O

Cpkg is 1pF

May 10, 2012


22

15 GND-PTH

700mV noise

coupling at

1.39GHz

IS THERE A RELATIONSHIP

BETWEEN RPD AND NOISE-

COUPLING?

May 10, 2012


23



Cdie 50pF per I/O

Cpkg is 4.7uF

May 10, 2012


24

3 GND-PTH



Cdie 50pF per I/O

Cpkg is 4.7uF

May 10, 2012


25

3 GND-PTH

40mV MORE noise coupling at 2.57GHz

for 3-GND-PTH than 15-GND-PTH



Cdie 50pF per I/O

Cpkg is 4.7uF

May 10, 2012


26

1 GND-PTH

20mV LESS noise coupling at 2.57GHz for 1-

GND-PTH than 15-GND-PTH

BUT 200mV wide-band coupling around 4.7GHz

EXAMPLE 3: STEP # 8

WHAT IS THE BENEFIT OF ON-

PCB DECAPS UNDER THE IC?

May 10, 2012


27

SSO Noise Source Extraction

Drivers Channel Receivers

Power Delivery Network

Current Probe @ VddQ pins

• SSO current is obtained by a combined

simulation of the power delivery network model

and the memory IO channel model

Combining Measured Icc(t) with FDTD

simulations to study the critical on-board-

decaps under the GPU

WORKSHOP EMEA

29

SSO Noise

fft

ifft

•Time-domain noise pattern directly imported into FDTD

solver

steady-state frequencies

Measured Dynamic-current profile Icc(t)

WORKSHOP EMEA

30

Board Geometry

11 cm

8 c

m

Signal

Ground

Signal

VDD

Ground

VDD

Stackup

board thickness: 1.57mm

Improting PCB layout of the Memory-

Channel

WORKSHOP EMEA

31

SSO Noise Source on Top Layer

31

IC

Noise sources

WORKSHOP EMEA

32

Decaps on Bottom Layer

32

decaps

WORKSHOP EMEA

33

Far-Field Radiation at 0.5 GHz

33

With Decaps Without Decaps

Reduction of 3-4 dB WORKSHOP EMEA

34

Far-Field Radiation at 1.0 GHz

34

With Decaps Without Decaps

Reduction of 3-4 dB WORKSHOP EMEA

35

Current Density at 0.5 GHz (1)

35

Without Decaps

WORKSHOP EMEA

36

Current Density at 0.5 GHz (2)

36

With Decaps

WORKSHOP EMEA

Conclusion

• Accurate modeling of Data-signals along with VddQ & VssQ

is important to capture VddQ-Noise Coupling to Data-Signals

• MOM is well suited to Model Data-Signals + VddQ + VssQ

including Return-Path-Discontinuity

• PDN Decoupling & GND-Stitching (Return-path-discontinuity)

impacts the Amount of VddQ-Noise coupling as well as the

Coupling-Frequency & Bandwidth of noise-coupling

• FDTD is best suited for SSO noise Modeling the impact of on-

PCB decaps to mitigate Radiated Emission caused by PCB

edge-emission due to noise pn PDN

May 10, 2012


37

Technology

Slow dancing pdn on memory-controller-packages may-10th_2012_hf_last