SDH MAPPING AND MULTIPLEXING

Niranjan BRTTC Mysore

SDH MAPPING AND MULTIPLEXING

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Generic Multiplexing Structure

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TRANSPORT OF ASYNCHRONOUS 2048 KBPS TRIBUTARIES ON STM–1 FRAME


Alternatives for Mapping 2048 Kbps Tributary on STM–1 Frame

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MUTIPLEXING PRINCIPLE

CONTAINER

SIGNAL

Container-n( n=1-4 ): A container is the information structure which forms the network synchronous information payload for a virtual container

2Mb

C-4

SIGNAL

C-3

SIGNAL

C-12

SIG

MUX PRINCIPLE: CONTAINERS(C-n)

Asynchronous Mapping of 2048 Kbps Tributary into VC–12

STRUCTURE OF C-12

R- Fixed stuff bytes make up for the required number of bytes in the container.

C & C’- Jusification control bytes

S- ` Justification opportunity bit

Fixed stuff bytes R make up for the required number of bytes in the container.

They are introduced after every 32nd byte of the tributary.

C and C’ bytes are the justification control bytes.

S is justification opportunity byte.

Construction of C–12

The bit structures of C, C’ and S bytes

C = C1 C2 0 0 0 0 R R

C’ = C1 C2 R R R R R S1

S = S2 I I I I I I I

I=Information bit of the tributary

VIRTUAL CONTAINER: VC-n

Virtual Container-n(VC-n):It is the information structure used to support path layer connections in the SDH.

Two types of VCs: Lower order VC-n(n=1,2)

Higher order Vc-n(n=3,4)

CONTAINER

P

O

H

C-12 to VC-12

C–12 container into VC–12 virtual container by adding the path overhead (POH) bytes.

The POH consists of a set of four bytes Vs, J2, Z6 and Z7, each of which is added sequentially before four C–12 containers.

V5 Byte Error detection, path error status and signal labeling . B1-even parity bit for all the odd numbered bits of the previous VC–12.

B2-even parity bit for all the even numbered bits of the previous VC–12.

B3-error indication which is sent back towards path originator if more than one error is detected by the parity bits.

B4- is Remote Failure Indication (RFI). It is set to ‘1’ if path failure is declared.

B 5 to 7 provide signal label, e.g. “010” indicates asynchronous tributary in the container. “

000” indicate unequipped VC–12.

B 8 is path FERF (Far End Remote Failure) indication when TU–12/TU–2 path AIS or signal failure condition is being received.

V5 Byte : It provides for error detection, path error status and signal labeling

J2 Byte 16Bytes

Repetitively transmit path access point identifier so that the

receiver can continuously identify the tributary.

J2 Byte

Z6 ByteFor providing monitoring function in Tandem

Z7 Byte

For future use

CONTAINERP

O

H

P

T

R

MUX PRINCIPLE: TU-n/ AU

•It is an information structure which provides adaptation between two layers: -Between lower and higher order path layers for TU

-Between higher order path layer and section layer for AU

POINTER is an indicator whose value defines the frame offset of a VC with

respect to the frame reference of the transport entity on which it is supported

Alignment from VC12- to TU-12

Formats of V1 and V2 bytes. V1 &V2 bytes indicate location of V5

N- NDF- New Data Flag =1001 , whenever new TU-12 comes it is inverted,

S- Trib type ,S=10 for TU12

IDID -10 bit offset of V5 bit from V2 byte

The four N bits are the New Data Flag (NDF)

Their usual value is 1001.

When new alignment of VC–12 is to be given, these bits are inverted and new pointer value is given in pointer bits.

The two ‘S’ bits indicate the tributary unit type. For TU–12, S bits are 10.

The point value is a 0–139 decimal number coded in 10 bits which are placed in the last two bits of V1 and 8 bits of V2 byte.

It is the offset of the V5 byte from the V2 byte.

V3 byte is used for negative justification opportunity,.

V4 Byte :This byte is reserved

Pointer Generation

Usually the pointer value will remain unchanged as indicated by NDF.

If due to some reason the pointer value needs to be changed, the NDF bits are inverted and the new value of the pointer takes effect.

If due to some reason the pointer value is to be incremented by one byte or reduced by one byte, positive or negative justification is required.

Pointer Generation

For positive justification the “ I “bits are inverted.

The positive justification opportunity byte which is next to V3 byte is filled with dummy bits and in the next tributary unit, the pointer value is incremented by one.

For negative justification, the D bits are inverted and V3 byte is filled with one VC–12 byte. The subsequent pointer is decremented by one in the next tributary unit.

TU–12 to TUG–12

Multiplexing

TU–12 to TUG–2 Multiplexing

Tributary units (TU–12) generated from three 2048 Kbps tributaries are multiplexed to form tributary unit groups (TUG–2)

TU–12s of different tributaries are already in phase synchronism. They are multiplexed byte by byte which results in 12x9 matrix of TUG–2

Note that first three bytes of TUG–2 in the upper left corner will contain the pointer bytes (V1, V2, V3, V4) of the respective TU–12s.

TUG–2 contains 108 bytes and is transported either in VC–3 or VC–4 container via TUG–3

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Multiplexing of TUG–2 into TUG–3

VC12=9x4=36byte

TUG2=3x 9x 4=108byte

For transporting TUG–2 in VC–4 containers,

Multiplexing of TUG–2 into TUG–3

As each TUG–2 contains three 2048 Kbps tributaries, 3x7x3 = 63 tributaries can be transported by a VC–4 container.

Multiplexing is done byte by byte.

TUG–3 contains 86 columns.

The first two column contain fixed stuff and

3 bytes long null pointer indicator (NPI).

TUG–3 can also contain VC–3 in which case

NPI bytes contain the pointer for VC–3.

First three bytes of TUG–2 contain the TU–12 pointer.

In TUG–3, these pointer appear in the first row of TUG–3.

The first bytes of columns 3 to 23 of TUG–3 contain these pointers. (3pointers per TUG2 *7 nos of TUG2=21)

Multiplexing of TUG–3 into VC–4


Three TUG–3 are multiplexed to form a VC–4 container

The first column is POH.

The next two columns contain fixed stuff.

The rest of VC4 is formed by byte multiplexing of 3 TUG–3s.

Note that all the pointer bytes of TU–12 are available in the first row in columns 10 to 72 of VC–4.


6th byte of POH, called H4 byte is for the location of pointer bytes of TU–12 are fixed and known but it is not known whether these bytes are V1 or V2 or V3 or V4.

This is indicated by H4 byte of POH.

Thus, in a VC–4 container, VC–12 container can be located by processing H4 and the pointer bytes of TU–12s.

H4 Byte Pointer Byte

X XXXX X00 V1

X XXXX X0I V2

X XXXX X10 V3

X XXXX XII V4

Multiplexing of AU–4 via AUG .The 9 bytes at the beginning of row 4 are allocated to the AU–4 pointer.

The remaining 9 rows by 261 columns is allocated to VC–4.

The phase of VC–4 is not fixed with respect to the AU–4.

The location of the first byte of the VC–4 with respect to the AU–4 pointer is given by pointer value.

The AU–4 is directly placed into AUG. One AUG gives STM–1.

Multiplexing of AU–4 via AUG

MULTIPLE SECTION OVERHEAD

REGENARATOR SECTION OVERHEAD

ADMINISTRATIVEUNIT POINT

9 x N COLOUM 261 x N COLOUM

1 -

35

-9

4

MULTIPLE SECTION OVERHEAD

REGENARATOR SECTION OVERHEAD

ADMINISTRATIVEUNIT POINT

9 x N COLOUM 261 x N COLOUM

1 -

35

-9

4

STM N FRAME STRUCTURE

622080Kbps

155520Kbps

51840Kbps

24488320Kbps

STM 4

STM 1

STM 0

STM 16

2.048 Mbps(E1)

1 2 3 32

32 Bytes

1 2 3 32VC-1235 Bytes

POH (Lower Order)

1 2 3 32C-1234 Bytes

Stuffing Bytes

Mapping of 2Mbps into STM – NMapping of 2Mbps into STM – N

TU-1236 Bytes

Pointer

9 Rows

4 Columns

TU 12 is arranged

Into Matrix of 9 X 4


TUG-2 9 Rows

12 Columns

9 Rows

4 Columns 4 Columns 4 Columns

TU-12 TU-12 TU-12

Multiplexing


EAGLE PHOTONICS

7 TUG-2s

Stuffing Bytes

86 Columns

84 Columns

TUG 3

X 7 TUG-2 TUG-3(multiplexing)


HOPOH

VC - 4

258 Columns

Stuffing Bytes

261 Columns

TUG - 3 TUG - 3 TUG - 3

86 Columns

X 3 TUG–3


EAGLE PHOTONICS

261 Columns

AU – 4 (Adding Pointer)

PO

H

Pay LoadAU Pointer

9 Columns

4 th Row

Pay LoadPO

H

VC - 4

261 Columns

9 rows


STM-1 frame structure

Mapping of VC–12 into VC–3 (2nd Alternate from E1 to VC-4)

Up to formation of TUG–2, the process is same.

From TUG–2, directly VC–3 is formed.

VC–3 is further processed to form STM–1

The pointer bytes of TU–12 are present in the first row of VC–3

H4 byte of POH indicates whether the pointer bytes are V1, V2, V3 or V4

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TUG-2 TO VC-3

Mapping of VC–3/VC–4 into STM–1

Three VC–3s or one VC–4 can be mapped into one STM–1 frame.


Mapping of Asynchronous 139264 Kbps into STM–1

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9 X 3

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139264 Kbps stream is first organised into

C–4 container of the size 9x260 (9 rows x 260cols).

By adding 1 column of path overheads to this container yields VC–4 which is of the size 9x261 (9 rows x 261 columns).

VC–4 is aligned into AU–4.

AU–4 is mapped into AUG.

One AUG gives STM–1.

Mapping 139264 Kbps tributary into VC–4

Each of the 9 rows is partitioned into 20 blocks consisting of 13 bytes each

In each row, one justification opportunity bit(s) and five justification control bits (c) are provided (Fig.3).

The first byte of each block consists of :

Either eight information bits (I), i.e. W bytes; OR

One justification control bit (c) plus five fixed stuff bits (R) plus two overhead bits (o), i..e x byte; OR

Six information bits (I) plus one justification opportunity bit(s) plus one fixed stuff bit (R), i.e. Z byte.

Alignment of VC–4 into AU–4VC–4 is aligned into AU4, by means of AU–4 pointer.

Multiplexing of AU–4 via AUG

The 9 bytes at the beginning of row 4 are allocated to the AU–4 pointer.

The remaining 9 rows by 261 columns is allocated to VC–4.


The location of the first byte of the VC–4 with respect to the AU–4 pointer is given by pointer value.

The AU–4 is directly placed into AUG. One AUG gives STM–1.

TRANSPORT OF ASYNCHRONOUS

34368 KBPS TRIBUTARIES ON STM–1 FRAME

Asynchronous Mapping of 34368 Kbps Tributary into VC–3

One 34368 Kbps tributary can be mapped into a VC–3, C–3 container is formed first by inserting justification and fixed staff bytes.

Justification makes the information bit stream and bytes synchronous to the SDH environment .

In addition to the VC–3 POH, the VC–3 consists of a payload of 9x84 bytes every 125 ms.

This payload is divided in three subframes, each subframe consisting of :

1431 information bits (I);

two sets of five justification control bits (C1,C20;

two justification opportunity bits (S1,S2);

573 fixed stuff bits (R).

Construction of VC–3 Container

VC–3 Path Overhead BytesThe VC–3 path overhead is located in the first column of 9 row by 85 column

VC–3 structure.

The POH consists of nine bytes denoted J1, B3, C2, G1, F2, H4, Z3, Z4, Z5

First AlternativeMapping via AU–3.

The three bytes at the beginning of row 4 are allocated to the AU–3 pointer, the remaining 9 rows by 87 column is allocated to the VC–3 and two columns of fixed stuff.

The byte in each row of the two columns of fixed stuff of each AU–3 shall be the same.

The phase of the VC–3 and two columns of fixed stuff is not fixed with respect to AU–3.

The location of the first byte of VC–3 with respect to AU–3 pointer is given by the pointer value. As shown the three AU–3s are byte interleaved in the AUG. One AUG gives STM–1.

Second AlternativeMapping via AU–4.

VC–3 is first aligned into TU–3. The TU–3 consists of the VC–3 with a 9 byte VC–3 POH and the TU–3 pointer.

The first column of the 9 row by 86 column TUG–3 is allocated to the TU–3 pointer bytes H1, H2, H3 and fixes stuff.

The phase of the VC–3 with respect to TUG–3 is indicated by the TU–3 pointer. .

Multiplexing of three TUG–3s into a VC–4

Multiplexing on AU–4 via AUG

The AU–4 consists of the VC–4 (Payload of 9 rows by 261 columns) plus 9 bytes at the beginning of row 4 (allocated to AU–4 pointer).


The location of the first byte of the VC–4 with respect to the AU–4 pointer is given by the pointer value. The AU–4 is placed directly in the AUG. One AUG gives STM–1

Pointers

AU–n Pointer

The AU–n pointer provides a method of allowing flexible and dynamic alignment of the VC–n within the AU–n frame

Dynamic alignment means that the VC–n is allowed to “Float” within the AU–n frame.

Thus, the pointer is able to accommodate differences, not only in the phases of the VC–n and the SOH, but also in the frame rates.

Synchronous Byte-interleaved Multiplexing

4 parallel and frame synchronised STM-1 SDH signals may be byte-interleave multiplexed together to form an STM-4 SDH signal at 622.08 Mb/s (4x STM-1 bit rate). Byte-interleaved multiplexing is accomplished by taking in turn, one byte from each input tributary and placing it in the higher speed output signal

Frame STM-16

Technology

SDH MAPPING AND MULTIPLEXING