Introducing SD 4.0 Device Controller

By Dennis McCarty

©Arasan Chip Systems Inc. 2011

©Arasan Chip Systems Inc. 2011

Arasan Chip Systems Total IP SolutionsSD 4.0 ImprovementsCore ArchitectureDeliverablesArasan Advantages

Arasan Total IP Solutions

©Arasan Chip Systems Inc. 2011

SD 4.0 Background

UHS-II PHY for faster throughput• 1.56 GB/s/lane at 52MHz• 300 MB/s overall

Differential signaling• D0+/- and D1+/-

Bus clock 208 MHz

Capacity from 32GBy to 2TBy

©Arasan Chip Systems Inc. 2011

©Arasan Chip Systems Inc. 2011

SD 4.0 Controller Architecture

©Arasan Chip Systems Inc. 2011

Compliance

Current to SD 4.0 (rev. April 2011)

Only announced product in the market

Deliverables

RMM (Reuse Methodology Manual) compliant Verilog

Configurable Behavioral models

Verification Suite & Test Cases

Documentation and Design Support

©Arasan Chip Systems Inc. 2011

Features

• Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design

• Software, Synthesis scripts and Test Environments

• Verification IP, ESL models

• HW Development Kits & Verification Platforms

• Design Services

April 13, 2023©Arasan Chip Systems Inc. 2011

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Total IP Solutions

April 13, 2023©Arasan Chip Systems Inc. 2011

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Benefits• Compliance across the standard• Single supplier – Single support• Guaranteed compatibility• Lowest overall cost and risk• Seamless integration from PHY to SW layers• Fastest cycle: MRD to SoC

Total IP Solutions