Logic gates presentation

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  • 1. Logic Gates & ItsLogic Gates & Its ApplicationApplication Presented by:Presented by: Rachna SinghRachna Singh (HOD.EC Dept)(HOD.EC Dept) SISTeC-E,Bhopal(M.P)SISTeC-E,Bhopal(M.P) SISTEC-E

2. AND Function Output Y is TRUE if inputs A AND B are TRUE, else it is FALSE. Logic Symbol Text Description Truth Table Boolean Expression AND A B Y INPUTS OUTPUT A B Y 0 0 0 0 1 0 1 0 0 1 1 1 AND Gate Truth Table Y = A x B = A B = AB AND Symbol SISTEC-E 3. OR Function Output Y is TRUE if input A OR B is TRUE, else it is FALSE. Logic Symbol Text Description Truth Table Boolean Expression Y = A + B OR Symbol A B YOR INPUTS OUTPUT A B Y 0 0 0 0 1 1 1 0 1 1 1 1 OR Gate Truth Table SISTEC-E 4. NOT Function (inverter) Output Y is TRUE if input A is FALSE, else it is FALSE. Y is the inverse of A. Logic Symbol Text Description Truth Table Boolean Expression INPUT OUTPUT A Y 0 1 1 0 NOT Gate Truth Table A YNOT NOT Bar Y = A Y = A Alternative Notation Y = !A SISTEC-E 5. NAND Function Output Y is FALSE if inputs A AND B are TRUE, else it is TRUE. Logic Symbol Text Description Truth Table Boolean Expression A B YNAND A bubble is an inverter This is an AND Gate with an inverted output Y = A x B = AB INPUTS OUTPUT A B Y 0 0 1 0 1 1 1 0 1 1 1 0 NAND Gate Truth Table SISTEC-E 6. NOR Function Output Y is FALSE if input A OR B is TRUE, else it is TRUE. Logic Symbol Text Description Truth Table Boolean Expression Y = A + B A B YNOR A bubble is an inverter. This is an OR Gate with its output inverted. INPUTS OUTPUT A B Y 0 0 1 0 1 0 1 0 0 1 1 0 NOR Gate Truth Table SISTEC-E 7. Exclusive-OR Gate X Y Z XOR X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 Z = X ^ Y xor(Z,X,Y) SISTEC-E 8. Exclusive-NOR Gate X Y Z XNOR Z 0 0 1 0 1 0 1 0 0 1 1 1 Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) SISTEC-E 9. Circuit-to-Truth Table Example OR A Y NOT AND B C AND 2# of Inputs = # of Combinations 2 3 = 8 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y SISTEC-E 10. Circuit-to-Truth Table Example OR A Y NOT AND B C AND 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 0 0 0 1 0 0 0 SISTEC-E 11. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 OR A Y NOT AND B C AND 0 0 1 0 1 1 1 1 SISTEC-E 12. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 OR A Y NOT AND B C AND 0 1 0 0 1 0 0 0 SISTEC-E 13. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 0 OR A Y NOT AND B C AND 0 1 1 0 1 1 1 1 SISTEC-E 14. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 1 0 OR A Y NOT AND B C AND 1 0 0 0 0 0 0 0 SISTEC-E 15. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 1 0 0 OR A Y NOT AND B C AND 1 0 1 0 0 0 0 0 SISTEC-E 16. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 1 0 0 0 OR A Y NOT AND B C AND 1 1 0 1 0 0 1 1 SISTEC-E 17. Circuit-to-Truth Table Example 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 1 0 1 0 0 1 0 OR A Y NOT AND B C AND 1 1 1 1 0 0 1 1 SISTEC-E 18. Circuit-to-Boolean Equation OR A Y NOT AND B C AND A B A C A = A B + A C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C Y 0 0 0 0 0 1 1} 1 1 } SISTEC-E 19. A - O - I Logic OR A Y NOT AND B C AND AND Gates INVERTER Gates OR Gates Other Logic Arrangements: NAND - NAND Logic NOR - NOR Logic SISTEC-E 20. NAND Gate Special Application INPUTS OUTPUT A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A B YNAND TNANDS S T 00 1 0 1 1 0 Equivalent To An Inverter Gate SISTEC-E 21. NOR Gate - Special Application S T 00 1 0 1 1 0 Equivalent To An Inverter Gate TS NOR A B YNOR INPUTS OUTPUT A B Y 0 0 1 0 1 0 1 0 0 1 1 0 SISTEC-E 22. NAND IMPLEMENTATION SISTEC-E 23. NOR IMPLEMENTATION SISTEC-E 24. Implementation of Half-Adder SISTEC-E 25. Basic Boolean Identities SISTEC-E 26. De Morgans Theorem ~(X & Y) = ~X | ~Y ~(X | Y) = ~X & ~Y NOT all variables Change & to | and | to & NOT the result SISTEC-E 27. Some Examples Example: use algebraic simplification rules to reduce ~xyz+~xy~z+xz ~xyz + ~xy~z + xz = ~xy(z+~z)+xz (distributive law) = ~xy(1)+xz (inverse law) = ~xy+xz (identity law) Example: xy+~xz+yz = xy+~xz+yz*1 (identity) = xy+~xz+yz*(x+~x) (inverse) = xy+~xz+xyz+~xyz (distributive) = xy(1+z)+~xz(y+1) (distributive) = xy(1)+~xz(1) (null) = xy*1+~xz*1 (absorption) = xy+~xz (identity) Example: (x+y)(~x+y) = ~x(x+y)+y(x+y) (distributive) = ~xx+~xy+xy+yy (distributive) = 0+~xy+xy+yy (inverse) = ~xy+xy+yy (identity) = y(~x+x+y) (distributive) = y(1+y) (inverse) = y(1) (identity) = y (idempotent) SISTEC-E 28. Karnaugh Map (K map) Method for minimizing logic Is used to represent the values of a function for different input values The rows and columns of the K-map correspond to the possible values of the function's input Each cell in the K-map represents a minterm (i.e. a three variables function has: xyz, xyz, xyz, xyz, xyz, xyz, xyz and xyz) SISTEC-E 29. K-map Example Lets consider (xy+yz) = xy + xz + yz Group together the 1s in the map: g1: xyz+xyz=xy(z+z)=xy g2: xyz+xyz = yz(x+x)=yz g3: xyz+xyz=xz(y+y)=xz To derive a minimal expression we must select the fewest groups that cover all active minterms (1s). (xy + yz)= xy + yz x y z x'y'+y'z'+yz' 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 SISTEC-E 30. IC USED FOR NAND Chip(7400) SISTEC-E Early integrated circuits were several gates on a single chip, you would connect this chip to other chips by adding wires between the pins To do ~(A*B) + ~(C*D) You would connect A and B to pins 7 and 6, C and D to 4 and 3, and send 5 and 2 to an AND chip 31. 7402 IC:NOR Gate Pin description of 7402 SISTEC-E 32. 7408:Two input AND gate Pin Description SISTEC-E 33. 7404:Hex Inverter Pin Description SISTEC-E 34. Thank You SISTEC-E