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a short slide on logic families in electronics along with some quick facts about them. you can contact anant @ http://anantshri.info
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INTRODUCTION TO LOGIC FAMILIES
What is a logic Family
It is the way to describe the internal circuitry of the I.C.
Types of logic Families
We have 7 Basic Logic Families
1) RTL – Resistor Transistor Logic
2) DTL – Diode Transistor Logic
3) IIL – Integrated injection Logic
4) TTL – Transistor – Transistor Logic (Ex 7400 & 5400
Series)
5) ECL – Emitter Coupled Logic (Ex 10000 series)
6) MOS – Metal Oxide Semiconductor
7) CMOS – Complementary Metal Oxide Semiconductor
(Ex. 4000 Series)
Presentation By Anant Shrivastava (E.I. Fourth Sem)
RTL & DTL – Not used in new design
But act as a useful starting point
RTL was the first Commercial Family
DTL is now Completely replaced by TTL TTL – It is a modified form of DTL
it is formed by replacing each diode with a transistor
Basic Gate is NAND
IIL,MOS – Used in Large Scale Integration ECL – Used in High Speed Operations
Basic Gate is NOR
CMOS – Where power requirement is low Basic Gate is inverter
Some Information on each Logic Family
Presentation By Anant Shrivastava (E.I. Fourth Sem)
Characteristics Fan-out – Maximum number of standard
load a gate can drive without disparity Power Dissipation – Power Required to operate the gate
Expressed in mW. Propagation Delay – Time taken by the signal to
propagate from input to output when a signal change occur
Noise Margin – Maximum Noise voltage that can be added to circuit without unwanted effect on output
(Two Types : - AC & DC Noise)
Represented in V and represent max level
Presentation By Anant Shrivastava (E.I. Fourth Sem)
Family Type
Voltage Supply
High Level Voltage Low Level Voltage
Range Typical Range Typical
TTL Vcc = 5 2.4 – 5 3.5 0 - 0.4 0.2
ECL VEE = -5.2 -0.95 – -0.7 -0.8 -1.9 – -1.6 -1.8
CMOS VDD = 3 – 10 VDD VDD 0 - 0.5 0
Common Logic Levels
Characteristic TableFamily Fan-out aPower
DissipationPropagation
delayNoise Margin
TTL 10 10 10 0.4
Schottky TTL 10 22 3 0.4
Low power Schottky TTL
20 2 10 0.4
ECL 25 25 2 0.2
CMOS 50 0.1 25 3
Presentation By Anant Shrivastava (E.I. Fourth Sem)