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This slides presents a excellent work on flash memory from Non-Volatile Systems Laboratory, University of California, San Diego.
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Outline
• Background• Some tests• Possible applications• Some extensions
Outline
• Background• Some tests• Possible applications• Some extensions
Background
• Flash manufacturers provide conservative and often vague guidelines about performance, energy consumption and reliability.
• The lack of detail complicates the design of systems which fully exploit flash memory’s capabilities.
Outline
• Background• Some tests• Possible applications• Some extensions
Test subjects
Characterizing Flash Memory: Anomalies, Observations, and Applications by Laura M. Grupp, Adrian M. Caulfield, Joel
Coburn etc.(MIRCO’09)
The tests
Quantify known and unknown idiosyncrasies• Performance• Energy Efficiency• Reliability
Read Latency
• The read latency varies little by manufacturer or chip, and are in good agreement with values from publicly available datasheets.
Erase Latency
• Erase latency exhibits a smaller gap, but manufacturer B enjoys an advantage for SLC and E for MLC.
Program Latency
• MLC chips have, on average, longer and enormously variable program latencies.
Program Speed Anomaly
• Programming speed varies dramatically between pages in MLC devices in a predictable pattern.
Performance Increase Anomaly
• Performance varies predictably as the devices begin to wear out.
Power
• The table presents peak power, average power, idle power, and per-operation energy for each operation.
Program Energy
• Fast and slow pages show a disparity similar to the one we observed for program time.
Reliability
• Flash memory can corrupt data in three main ways: wear-out, program disturb and read disturb.
• 10 erase-program-read cycles + 990 erase-program.
• 1 million erases for SLC and 100,000 erases for MLC.
Error Rates
• The difference between SLC and MLC is stark.
Disparity in MLC
• MLC chips show large variation in error rates among pages in a single block.
Program Disturb
• Erase a block and repeatedly program half of one page to 0.
Read Disturb
• Write a test pattern to several blocks on the flash chip and repeatedly read the pattern back.
Summary
• Fast pages and slow pages in MLC• High energy-consumption pages and low
energy-consumption pages in MLC• Better program performance as wear out for
SLC and MLC• High error-rate pages and low error-rate pages
in MLC• Program disturb and read disturb
Outline
• Background• Some tests• Possible applications• Some extensions
A variation-aware FTL
• Mango adds a priority to incoming IO request and it will do its best to use fast pages for the high-priority writes.
• This variation-aware FTL is evaluated in two scenarios: Swap&Netbook.
• For Swap, it can significantly increase responsiveness for swap requests.
• For Netbook, it can slightly reduce the energy drain on the battery.
Flash-aware data encoding
• Womcode is a coding techniques makes rewriting wom possible!
• Effective lifetime:- SLC: 2*(2/3) = 33% increase- MLC: (2*(2/3) + 1)*(1/2) = 17% increase
Outline
• Background• Some tests• Possible applications• Some extensions
Gordon
• A system architecture for data-centric applications that combines low-power processors, flash memory, and data-centric programming.
• Performance & Reduced Power Consumption
Gordon: Using Flash Memory to Build Fast, Power-efficient Clusters for Data-intensive Applications by Adrian M.
Caufield Laura M. Grupp and Steven Swanson(ASPLOS’09)
Gordon Node
• 256GB flash storage, a flash storage controller, 2GB of ECC DDR2 SDRAM, a 1.9Ghz Intel Atom processor and other supporting circuitry.
Gordon Enclosure
• A enclosure holds 16 nodes(4TB storage) and provides 14.4GB/s of aggregate IO bandwidth.
Q & A
Thank you !
