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i3070 Hidden Gems
PLD ISP (IEEE 1532)
Agenda Overview of In-System Programming on the
Agilent 3070
Details of ISP Development for XTP Cards
Definitions / Glossary PLD
Programmable Logic Device
CPLD Complex Programmable Logic Device
Bitstream Binary sequence used to program the PLD (usually very long)
JEDEC, JTAG, SVF, STAPL, Jam, JBC Standards and formats used to describe the bitstream required to program a PLD.
Boundary Scan Test Tool used to apply the bitstream to the device being programmed.
TCK
Boundary Scan’s PLD-ISP Overview
TDI
Bitstream 1010101
U1
Core
Logic
TEST ACCESS PORT
CONTROLLER
(TAP)
TMS = U1 Program
U2 Bypass .
TEST ACCESS PORT
CONTROLLER
(TAP)
TDO to TDI
101010
U2
Core
Logic
TMS = U1 Bypass .
U2 Program
1010101
1010101
TDO
Bitstream 1010101
Two Methods to Program PLD-ISP Requires XTP or XT Control Cards
Turn-on
&
Debug
Get Design Files
&
Design Tools
Finish the
Board Consultant
Description
Use Test
Consultant to
generate VCL
and JBC files
Turn-on &
Debug Tests
Get Design
Files & Create
Bitstream Files
Convert
Bitstream to
PCF/VCL
&
Compile
Add Pull-up And
Pull-down
Resistors in Test
Fixture
If ECO -
Regenerate
Bitstream File
and Convert
to PCF
Next Device
NO
YES
Device
Program
OK ?
XT XTP
PLD Programming on 3070 XTP vs XT Control Cards
XTP/XTPA Control Card XT Control Card
Device Bitstream
File Size
JBC File
Size
JBC
Compile
Time
JBC Run
Time
PCF File
Size
PCF
Compile
Time
PCF Run
Time
Altera
EPC2
64Kbytes
STAPL
52KB 125s 46s/45s 194MB
30 Files
80 min 131s/88s
Lattice 2x
GDX160V
207KB SVF 260KB 80s 12s/11s 5.1 MB
3 files
4 min 23s/19s
Altera 4x
EPM7128s
2.3MB
SVF
33KB 30s 23s/22s 81.5 MB
30 Files
4.5 hours 49s/15s
XTP Development Process - Overview
Turn-on
&
Debug
Get Design Files
&
Design Tools
Use BT-BASIC to edit the STAPL and/or VCL and recompile new test.o and JBC files
Finish the
Board Consultant
Description
Use Test
Consultant to
generate VCL
and JBC files
Use Vendor Tools to create a Bitstream file: STAPL, SVF, JAM or JBC
Create a setup-only library for the PLD test
Create test executables
GET DESIGN FILES
&
DESIGN TOOLS
Finish the
Board Consultant
Description
Use Test
Consultant to
generate VCL
and JBC files
Turn-on
&
Debug
Get Design Files Some Design Tools
Some of the other Vendor Tools
PLD ISP Development Process Follow the process with this example chain
Design Engineer’s Files:
u4bitstream (Vendor A)
u5bitstream (Vendor A) u6bitstream (Vendor A) u9bitstream (Vendor B)
U4
TAP
U5
TAP
U6
TAP
U9
TAP
TMS TCK
TDI TDO
TDI to TDO
PLD ISP Development Process Use Vendor Tools to Convert the Design Files to a standard format
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Finish the
Board Consultant
Description
u4bitstream (SVF)
u5bitstream (SVF) u6bitstream (SVF) u9bitstream (STAPL)
Agilent 3070 Advanced Digital Module 7: PLD ISP
PLD ISP Development Process Create a setup-only library
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Finish the
Board Consultant
Description
pld isp ! sequential
vector cycle 160n
receive delay 120n
assign TCK to nodes “TCK”
assign TMS to nodes “TMS”
assign TDI to nodes “TDI”
assign TDO to nodes “TDO”
family Flash_3V3
inputs TCK, TMS, TDI
outputs TDO
scan tap
tck TCK
tdi TDI
tms TMS
tdo TDO
end scan tap
u4bitstream (SVF)
u5bitstream (SVF) u6bitstream (SVF) u9bitstream (STAPL)
S
“custom_lib/pld_chain”
PLD ISP Development Process Enter Node Library, Internal Devices & Mark Nodes Critical
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Finish the
Board Consultant
Description
u4bitstream (SVF)
u5bitstream (SVF) u6bitstream (SVF) u9bitstream (STAPL)
PLD ISP Development Process Use Test Consultant to create setup-only tests
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Use Test
Consultant to
generate VCL
and JBC files
Finish the
Board Consultant
Description Yes
Yes
No
Convert
to STAPL
source file
Compile
VCL to
test.o
Compile
STAPL to
JBC object
SVF File
?
No First
Compile
?
Test Consultant:
u4, u5, u6, u9 , pld_chain
u4bitstream (SVF)
u5bitstream (SVF) u6bitstream (SVF) u9bitstream (STAPL)
u4_pld.o
u5_pld.o
u6_pld.o
u9_pld.o
pld_chain.o
PLD ISP Development Process Manually edit the VCL Tests to point to bitstream files
Get Design Files
&
Design Tools
Finish the
Board Consultant
Description
Edit the individual tests:
! Add reference to the bitstream file(s) SVF: program Program_U4
file “u4bitstream.svf” svf
end program
unit “Program U4”
play Program_U4
end unit
! Add reference to the bitstream file(s) STAPL: program Program_U9
file “u9bitstream.stapl” stapl
!! program time 60 sec
end program
unit “Program U9”
play Program_U9 action Program
end unit
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Use Test
Consultant to
generate VCL
and JBC files
PLD ISP Development Process Compile to create .jbc files and test executables
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Use Test
Consultant to
generate VCL
and JBC files
Finish the
Board Consultant
Description Yes
Yes
No
Convert
to STAPL
source file
Compile
VCL to
test.o
Compile
STAPL to
JBC object
SVF File
?
No First
Compile
?
u9bitstream.stapl u9bitstream.stapl.jbc u9_pld.o
u5bitstream.svf u5bitstream.svf.stapl u5bitstream.svf.stapl.jbc u5_pld.o
u6bitstream.svf u6bitstream.svf.stapl u6bitstream.svf.stapl.jbc u6_pld.o
, u5 and u6 , u9 u4bitstream (SVF)
u5bitstream (SVF) u6bitstream (SVF) u9bitstream (STAPL)
, pld_chain
pld_chain.o
compile u4
u4bitstream.svf u4bitstream.svf.stapl u4bitstream.svf.stapl.jbc u4_pld.o
new executables
PLD ISP Development Process Manually edit the testplan
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Use Test
Consultant to
generate VCL
and JBC files
Finish the
Board Consultant
Description
In testplan: test “digital/u4”
test “digital/u5”
test “digital/u6”
test “digital/u9”
test “digital/u4_pld”
test “digital/u5_pld”
test “digital/u6_pld”
test “digital/u9_pld”
! test “digital/pld_chain”
. . .
PLD ISP Development Process Debug Tools
Turn-on
&
Debug
Use Test
Consultant to
generate VCL
and JBC files
Get Design Files
&
Design Tools
Use Test
Consultant to
generate VCL
and JBC files
Finish the
Board Consultant
Description
Always fails: • Verify order of devices entered in the chain
description is correct and complete
• Verify Instruction Register Lengths are
correct (for parts from other vendors)
Intermittent: • Run as fast as possible, but slow vector cycle
time if test is intermittent
• Insure Boundary Scan signals are “clean,”
especially TCK.
• Reset drive levels, slew rates,...
General Debug: • Add print statements in the STAPL to isolate
point of failure.
print “Passed line 3000 in STAPL”; print “Finished Bulk Erase”;
PLD ISP Engineering Change Process What to do when the design file changes
• Create a new bit-stream file for the new design using the Vendor’s tool as before
• If the bitstream file name is different, modify the VCL test to point to the new bitstream file name
• Compile the VCL test. This will create a new JBC object file and test object file
• Debug the new version of the test to make sure it works correctly.
– If there is a problem, check to see that the bitstream file was created correctly (i.e., correct chain definition, etc).
Thank you!
For more information on PLD ISP or Flash ISP testing, please contact your local Agilent representative
Or navigate to
www.agilent.com/find/i3070
i3070 Advanced Digital Training
www.agilent.com/contactus
THE END