ANNAMACHARYA INSTITUTE OF TECHNOLOGY & SCIENCES

ECE-DEPARTMENT

Design of High Performance

MAC Unit

1. SHIVA SHANKER BEERAVELLI : 10T81A04482. PALUSA KRANTHI KUMAR GOUD : 10T81A04173. G.SHIVA NARAYANA REDDY : 10T81A0449

Guide: Mr. K.ASHOK KUMAR

HOD-ECE DEPT.

INTRODUCTION:

With the recent rapid advances in multimedia and communication systems,

real-time signal processing like audio signal processing, video/image processing, or

large-capacity data processing are increasingly being demanded.

The multiplier and multiplier-and-accumulator (MAC) are the essential

elements of the digital signal processing such as filtering, convolution,

transformations and Inner products

Power dissipation is recognized as a critical parameter in modern the objective

of a good multiplier is to provide a physically compact, good speed and low power

consuming chip.

AIM Of the Project:

MAC unit is used for high performance digital signal processing systems. The

DSP applications include filtering, convolution, and inner products.

multiplier-and-accumulator (MAC) for high speed and low-power by adopting the

new SPST implementing approach.

Therefore the functionality of the MAC unit enables high-speed filtering and

other processing typical for DSP applications.

MAC is a integrating circuit that reduces the power consumption , delay & area.

MAC INTRODUCTION:

MAC unit performs important operation in many of the digital signal

processing (DSP) applications.

The multiplier is designed using modified Wallace multiplier and

the adder is done with carry save adder.

The total MAC unit operates at 217 MHz. The Total power dissipation is

177.732mW.

In this project we used Modelsim for logical verification, and further

synthesizing it on Xilinx-ISE tool

MAC basic architecture:

A MAC unit consists of a multiplier & an accumulator containing the sum of the previous successive products.

The MAC inputs are obtained from the memory location and given to the multiplier block.

The design consists of 64 bit modified Wallace multiplier.

128 bit carry save adder and a register/ accumulator.

The output of carry save adder is 129 bit i.e. one bit is for the carry

(128bits+ 1 bit). Then, the output is given to the accumulator register.

The accumulator register used in this design is Parallel In Parallel Out

(PIPO).

The output of the accumulator register is taken out or fed back as one of

the input to the carry save adder.

Wallace tree: A Wallace tree is an  efficient hardware implementation of a digital circuit that multiplies two integers.

Generally in conventional Wallace multipliers many full adders and half adders are used in their reduction phase

CARRY SAVE ADDER:

A carry-save adder is a type of digital adder, used in computer micro architecture to compute the sum of three or more n-bit numbers in binary. It differs from other digital adders in that it outputs two numbers of the same dimensions as the inputs, one which is a sequence of partial sum bits and another which is a sequence of carry bits.

The carry save adder block is same as the full adder

Carry Save Adder (adding 2 numbers)

In this design 128 bit carry save adder is used since the output of the multiplier is 128 bits .

The entire sum can be calculated by shifting the carry sequence left by one place and then appending a 0 to most significant bit of the partial sum sequence.

a carry-save adder produces all the output values in parallel, resulting in the total computation time less than ripple carry adders. So, Parallel In Parallel Out (PIPO) is used as an accumulator in the final stage.

RESULT:

Output at reset condition:

1) digital signal processing (DSP) applications

a. Signal filtering

b. convolution.

c. Decreasing number of inner products.

2) Optical communications.

3) Multimedia image processing.

4) real-time signal processing like audio signal processing, video/image

processing, or large-capacity data processing

 

Applications

Advantages:The MAC unit operates completely independent of the CPU, it can process data separately and there by reduce CPU load. The application like optical communication systems which is based on DSP , require extremely fast processing of huge amount of digital data

Area , Delay Report & power dissipation of Different MAC unit

Since the delay of 64 bit is less, this design can be used in the system

which requires high performance in processors involving large number of

bits of the operation. The MAC unit is designed using Verilog-HDL and

synthesized in Cadence 180nm RTL Complier.

 

Conclusion: