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Quiescent Current Testing of CMOS Data ConvertersData Converters

Research PresentationResearch PresentationBy

Siva Yellampalli

Date: November 5, 2008 (2:00 – 4:00 PM), Fall 2008 Room: EE117

Department of Electrical and Computer EngineeringLouisiana State University

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Outline of the PresentationIDDQ Testing methodologyTesting data converter circuitsPh i l f lt d f lt i j ti t h iPhysical faults and fault injection techniqueFuture trends of IDDQ testingCircuit under testBICS for IDDQ testingBICS for ΔIDDQ testingCombined IDDQ IDDT and oscillation test methodologyCombined IDDQ, IDDT and oscillation test methodology.IDDT current testingOscillation based testingC l iConclusion

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Outline of the PresentationI Testing MethodologyIDDQ Testing MethodologyNeed for Testing Data Converter CircuitsPhysical Faults and Fault Injection TechniqueIDDQ BICS DesignFuture trends of IDDQ testingΔIDDQ BICS TestingΔIDDQ BICS TestingCombined IDDQ, IDDT and Oscillation Test MethodologyIDDT Current TestingOscillation TestingOscillation TestingConclusion

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I Testing MethodologyIDDQ Testing MethodologyVDD VDD

V

Q1 Q3

IDDQ=0

Vin Vout

Q2 Q4

Without fault With fault

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Block Diagram of IDDQ TestingVDD

PMOSBLOCK

INPUTS

NMOSBLOCK

INPUTS

OUTPUT

CUT

BICS

PASS/FAIL

VSS

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Need for Testing of Data ConverterNeed for Testing of Data Converter Circuits

Photolithographic processParticle related defects have been observed as major

f d f t i i d i l i itcause of defects in mixed signal circuits.

Physical failures-bridges-opens and-gate oxide shorts (GOS)gate oxide shorts (GOS).

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Bridging FaultsVDD

Bridging faults -short circuit faults in i t t d i it

V

integrated circuits. -can appear either at the logical output of a gate or at

VA

V0

Bridge 1: Drain-gate

g p gthe transistor nodes internal to a gate.

VB

Bridge 2 : Gate source

Bridge 3 : Drain-source

Bridge 2 : Gate-source

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B id i F lBridging FaultsDifferent bridging faults*: (a) shorting of seven metalshorting of seven metal lines caused by unexposed photo resist, (b) shorting of four metal lines by solid state particle on the metalstate particle on the metal mask, (c) shorts and breaks of metal lines caused by scratch in the photo resist, (d) short among multiple(d) short among multiple metal lines by a metallization defect of 1um in size, (e) short between two aluminum lines due totwo aluminum lines due to metallization defects, and (f) inter layer short between two aluminum interconnects in 0 5 um technologyin 0.5 um technology.*R. Rajsuman, “IDDQ testing for CMOS VLSI,” Proc. of the

IEEE, vol. 88, no. 4, 2000, pp. 544-566.

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Gate Oxide FaultsGate oxide shorts

-occur frequently in CMOS technology.

-reasons are breakdown of the t id d th f t igate oxide and the manufacturing

spot defects in lithography and processes on the active area and polysilicon masks

Gate Oxide defects: (a) gate-oxide short to N+ diffusion*, and

polysilicon masks.

,(b) gate oxide pin hole causing cell word line leakage memory+ .

*C.F. Hawkins and J.M. Soden, “Reliability and electrical properties of gate oxide shorts in CMOS ICs,” Proc. Int. Test Conf., 1986, pp. 443- 451.

+A. Chan, D. Lam, W. Tan and S.Y. Khim, “Electrical failure analysis in high density DRAMs,” Proc. Int. Test Conf., 1998, pp. 43-52.

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Open Faults

(a) a foreign particle causing a lineopen and a ling thinning*

(b) A contaminated particle causing 7-(b) A contaminated particle causing 7line opens* and

(c) SEM picture of defect whichcaused open in metal 2 and a shortpin metal 1+.

*W. Maly, “Realistic fault modeling for VLSI testing,” IEEE Design Auto. Conf., 1987, pp. 173-180.

+J. Khare, S. Griep, H.D. Oberle, W.Maly, D.S. Landsiedel, U. Kollmer and D. M. H. Walker, “Key attributes of an SRAM testing strategy required for effective process monitoring,” IEEE Int. workshop on Memory Testing, 1993, pp. 84-89.

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Fault Injection TechniqueFault Injection Technique Example: Fault-Injection Transistor (N-

MOSFET) at Inverter OutputMOSFET) at Inverter OutputVDD

VE

G

D SME(4.5/1.6)

V0

VE

D

ME

(4.5/1.6)

VI

EE

G

S

VSS FIT

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Outline of the PresentationIDDQ Testing methodologyNeed for Testing data converter circuitsPh i l f lt d f lt i j ti t h iPhysical faults and fault injection techniqueIDDQBICS designFuture trends of IDDQ testingDDQ gBICS for ΔIDDQ testingIPS current testingOscillation based testingOscillation based testingConclusion

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Outline of the PresentationI Testing MethodologyIDDQ Testing MethodologyNeed for Testing Data Converter CircuitsPhysical Faults and Fault Injection TechniqueIDDQ BICS DesignFuture trends of IDDQ testingΔIDDQ BICS TestingΔIDDQ BICS TestingCombined IDDQ, IDDT and Oscillation Test MethodologyIDDT Current TestingOscillation TestingOscillation TestingConclusion

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VDD(+2.5V)

VE3M5

M7

M8

VSS

XFIT 3

VE2

XFIT 2

VSS

VE6

XFIT6

VSS

CMOS Amplifier

V+

VBIAS

V-

CC

M1 M2

M11 VSS

VE5 XFIT 5

VOUT

CMOS Amplifier (CUT)

(XFIT8)

VE1M3 M4

M6M10

VSS(-2.5V)

XFIT 1 VSSVE4

XFIT 4

VE7 XFIT 7

M5

M6

VDD

VDD

VDDVSS

5.6/1.6

11.6/1.6

BICS

IREF EXTIDEF

IDEF - IREF OUTPUT

M0M1 M2

M3M4

SS

VSS

36/1.6

92/1.6

6.4/1.6

3.2/1.6100/1.6

IREF ( PASS/ FAIL )

VENABLE VSS36/1.6

100/1.6400/1.6

VSS(-2.5V)

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Si l t d BICS O t t d M d I fSimulated BICS Output and Measured IDDQ for Defects

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Layout of Built-in Current Sensor

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BICS Showing PASS/FAIL Output from HP1660CS Logic Analyzer Corresponding to Fault M5DSS

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Future Trends of IDDQ TestingThe theoretical basis of IDDQ testing is based upon estimation of defect free current in the circuit and then setting a limitdefect-free current in the circuit and then setting a limit (threshold) above which a circuit is considered defective.

M th d f tti th h ld li itMethods for setting threshold limit- 1μA is considered defect free any number from as low as 10 μA to 100 μA is considered as threshold limit.

- Due to large number of devices, the distribution of the measured current is expected to be Guassian. Due to statistical variations IC’s up to mean +3σ are consideredstatistical variations, IC s up to mean +3σ are considered defect free. A limit higher than mean +3σ is assumed, above which IC’s are considered defective.

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Future Trends of IDDQ TestingWhen the density of the defect free and defective currentWhen the density of the defect-free and defective current are separated from each other, clear distinction between the good and the defective ICs can be made.In submicron CMOS technology the mean of the distribution of defect free current increases and approaches the I threshold limit (set from earlierapproaches the IDDQ threshold limit (set from earlier technology)Changing the threshold limit to higher number does not resolve the issue because with high leakage current the change in defect-free and defective current is miniscule and unidentifiable.and unidentifiable.

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Future Trends of IDDQ Testing

Sub threshold leakage current.

⎞⎛ ⎞⎛⎞⎛ VV

⎟⎟⎟⎞

⎜⎜⎜⎛

−=⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛ −

t

dsthgs

vV

SVV

sub kI exp1exp 10ln/

⎟⎟⎠

⎜⎜⎝

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F t T d f I T tiFuture Trends of IDDQ Testing

D i M th dDesign Methods- Reduced temperature- Substrate biasSubstrate bias- Switched source impedance leakage reduction technique

- Dual threshold method Testing methods- ΔIDDQ TestingΔIDDQ Testing - Power supply current testing- Oscillation testing method

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Future Trends of I TestingFuture Trends of IDDQ TestingΔIDDQ Testing of CMOS ICs

relative methods of the offstate current is taken instead of- relative methods of the offstate current is taken instead of absolute ones for fault detection.

Power supply current based testing method.pp y g-variation of AC ripple in the supply current under the application of AC input stimulus is used for fault detection.

O ill ti b d t ti th dOscillation based testing method.- Converting the CUT is into an oscillator using feedback.- Output oscillation frequency is monitored for faults in theOutput oscillation frequency is monitored for faults in the

CUT.- Needs no test signal generation, uses simple measurement

and has high fault coverage.

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Outline of the PresentationIDDQ Testing methodologyTesting data converter circuitsPh i l f lt d f lt i j ti t h iPhysical faults and fault injection techniqueFuture trends of IDDQ testingCircuit under testBICS for IDDQ testingBICS for ΔIDDQ testingIDDT current testingIDDT current testingOscillation based testingConclusion

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Outline of the PresentationI Testing MethodologyIDDQ Testing MethodologyNeed for Testing Data Converter CircuitsPhysical Faults and Fault Injection TechniqueIDDQ BICS DesignFuture trends of IDDQ testingΔIDDQ BICS TestingΔIDDQ BICS TestingCombined IDDQ, IDDT and Oscillation Test MethodologyIDDT Current TestingOscillation TestingOscillation TestingConclusion

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∆I BICS Design and Testing∆IDDQ BICS Design and TestingDDV

4-Bit BinarySynchronous

VTG TG1

DischargingInput to

Discharging input to

comparator Comp.output 4-Bit

OutputCount

AnalogI/P

A

yCounter

B

TG2CompOutput Pulse

Input toComparator

outputpulse

11

Vref

CUTDDQI

C

gComp I/P

CLK I/P

C

D

00

Vref

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Layout of BICS

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Comparator Design2.5VVDD =

M3

M10M8

M4

M126.6/0.6 6.6/0.6 5.4/0.6

3/0.6 3/0.6

M3 M4

0 9/0 6 0 9/0 6

OUTVNN2

N1

Inv1NEGV POSVM2

M11M9M6M5

M1

M1330/0.6 30/0.6

0.9/0.6 0.9/0.6

3.9/0.6 1.5/0.6 1.5/0.6

M712/0.6

GND

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Analog-to-Digital Converter

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Analog-to-Digital Converter

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3-BIT Flash Architecture ADC1.5R 3-BIT flash architecture

2.5v

R

R

3 BIT flash architecture based ADC.Designed for operation at 2 5 V in 0 5 μm n well

2N-1 to Nencoder

Output Digitalword

R

R

2.5 V in 0.5 μm n-well CMOS technology.The various blocks are

R

R

- voltage reference- resister ladder- seven comparators

R

seven comparators- 8:3 encoder

0.5R

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3-BIT Charge Scaling Architecture DACDesigned for operation at

R 0 5 F0.5pF1pF2pF VOUT

Designed for operation at2.5 V.

Building Blocks: Reset 0.5pFp g

- Voltage Reference

- Binary Switches

D2 D1 D0

- Binary Switches

- Scaling Network

O ti l A lifiVReference - Operational Amplifier

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Low Voltage Operational AmplifierLow Voltage Operational Amplifier DesignDouble Ended

VDD

Bulk DrivingCircuitry

BiasingCircuitry

DifferentialInput Stage

Double Endedto Single EndedConversion Stage

High SwingCircuitry

SecondStage(Class AAmplifier)

M1 M2

M3M4

M11

M12

M14M17

M19M21

M23

ONV

TON VV +

TON VV +2M15TON VV +

VPOSVNEG

VOUT

M1 M2

M5

M6 M7

M8 M9

MR

M11

Cc

Mb

M20 M22

TON VV +

M5 M8M10 M13

M16M18

M20 M22

Note: For the P-MOSFETS the substrate is connected to VDD

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Layout of Op-Amp

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12-bit ADC with Induced Faults12 bit ADC with Induced Faults

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Simulation of the Comparator With no Fault

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Chip layout of 12 bit ADC in 40 pinChip layout of 12-bit ADC in 40-pin Padframe

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Microphotograph of Fabricated Chip

ΔIDDQ BICSPart of 12-bit ADC

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Experimental Results

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Simulated Count Values from SPICE andSimulated Count Values from SPICE and Experimental Values for all the Five

FaultsFaults

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Equivalent FaultsVDD

FIT FIT

RR

M17 M19

INPUT OUTPUT

FITFIT

FIT

RR

M18 M20

VSS

VSUBSTRATESUBSTRATE

Low Voltage op-amp.

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Bulk DrivingCircuitry

BiasingCircuitry

DifferentialInput Stage

Double Endedto Single EndedConversion Stage

High SwingCircuitry

SecondStage(Class AAmplifier)

M3M4

M12

M14M17

M19M21

VDDAmplifier)

ONVTON VV +2M15

TON VV +

VPOSVNEG

VOUT

M1 M2M6 M7

MR

M11

M12

Cc

Mb

M23TON VV +

M5 M8 M9M10 M13

M16M18

M20 M22

Note: For the P-MOSFETS the substrate is connected to VDD

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Scan Path Test

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VCO Output ∆I BICS Design andVCO Output ∆IDDQ BICS Design and Testing

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Comparator DesignComparator Design

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12-bit Digital-to Analog ConverterCapacitor Array Architecture Storage Unity GainCapacitor Array Architecture

Unity GainOPAMP

TG Switch StorageCapacitor

yBuffer

LSB Array MSB Arrayc64

VoHC

LSB Array MSB Array

2CC 32C16C4C 8CC 2C 4C 8C 16C 32C C

63

Output of Multiplexer

Sample and Hold InputCircuitry To Generate Digital Input Word

REFV

Control Signal

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Layout of a 12 Bit DACLayout of a 12-Bit DAC

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Deviation (%) in Frequency Output of BICSDeviation (%) in Frequency Output of BICS Under Fault Injection Conditions

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Outline of the PresentationI Testing methodologyIDDQ Testing methodologyTesting data converter circuitsPhysical faults and fault injection techniqueFuture trends of IDDQ testingCircuit under testBICS for IDDQ testingBICS for IDDQ testingBICS for ΔIDDQ testingCombined IDDQ, IDDT and oscillation test methodologymethodology.IDDT current testingOscillation based testingC l iConclusion

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Outline of the PresentationI Testing MethodologyIDDQ Testing MethodologyNeed for Testing Data Converter CircuitsPhysical Faults and Fault Injection TechniqueIDDQ BICS DesignFuture trends of IDDQ testingΔIDDQ BICS TestingΔIDDQ BICS TestingCombined IDDQ, IDDT and Oscillation Test MethodologyIDDT Current TestingIDDT Current TestingOscillation TestingConclusion

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Test methodologyVDDVDD

CUTInput Functional Output

Additional fOSC

Pass/Fail

BICSAdditionalFeedbackCircuitry

OSC

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IDDT based testing methodologyIDDT based testing methodology

AC ripple in the power supply current IDDT, passing pp p pp y DDT, p gthrough VDD under the application of an AC input stimulus is measured. Th i t i l h ld d ti bl t fThe input signal should produce a noticeable amount of difference between the IDDT of each faulty and fault-free cases hence a square wave is used.Tolerance limit for the magnitude of IDDT is set as ±5% such that it takes in account the deviations of significant technology and design parameterstechnology and design parameters.If the magnitude of IDDT with fault falls out of this tolerance range the fault is detected.g

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IDDT based testing methodologyV

A small resistor is used to th lt di VDD

VR100 Ω

sense the voltage corresponding to IDDT.

This resistor shows i i ifi t i ti CUT

PMOSBLOCK

insignificant variation on CUTs performance.

Input signal to the CUT is 4 V 5 kH 1 kH BLOCK

NMOS

INPUTOUTPUT

p gp-p, 5 kHz or 1 kHz square wave.

BLOCKCUT

Block diagram of power supply current, IDDT

VSS

supply current, IDDTbased testing

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Two stage CMOS op-ampVDD(+2.5V)

VE3

M5

M7M8V

XFIT 3

VXFIT 2

VXFIT 6

VSSVE2

VSS

VE6VSS

V+

VBIAS

V-

CC

M1 M2M11

VSS

VE5 XFIT 5

VOUT

VE1

CC

M3 M4

M6

M10XFIT 1

VSS

VE4

XFIT 4

VE7XFIT 7

VSS

VSS(-2.5V)

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Spice Simulated IPS for CUT 1

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Measured IDDT (AC Ripple) for CUT1DDT ( pp )

For No Fault, Faults 4 and 6 are Faults 4 and 6 are injected one at a time for CUT

Input Voltage

Input is a square wave 4 V p-p at 5 kHz

Voltage Corresponding kHz.

IDDT is 74 µA

Corresponding to IPS

sensed across a 100Ω resistor

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SPICE Si l t d nd E p i nt l R lt fSPICE Simulated and Experimental Results for CUT 1

Fault Number IPS in µA(Si l t d)

IPS in µA (E i t l)(Simulated) (Experimental)

No fault 74 74

F lt 1 804 830Fault 1 804 830

Fault 2 95 130

Fault 3 93 120

Fault 4 74 74

Fault 5 170 -

Fault 6 73 74

Fault 7 156 268

+Loss of IPS.

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Oscillation based test methodConsists of converting theConsists of converting the CUT into an oscillator using passive/ active components in the

R2 R1

components in the feedback. fOSC

RC

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Two stage CMOS op-ampVDD(+2.5V)

VE3

M5

M7M8V

XFIT 3

VXFIT 2

VXFIT 6

VSSVE2

VSS

VE6VSS

V+

VBIAS

V-

CC

M1 M2M11

VSS

VE5 XFIT 5

VOUT

VE1

CC

M3 M4

M6

M10XFIT 1

VSS

VE4

XFIT 4

VE7XFIT 7

VSS

VSS(-2.5V)

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FFT Simulations for Evaluating theFFT Simulations for Evaluating the Oscillation Frequency of the CUT Oscillator

0

1

2

(V)

-2

-1

1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05

Volta

ge, (

-3T ime (s)

The natural oscillationThe natural oscillation frequency (f NAT) was observed to be 875 kHz.

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Monte-Carlo AnalysisN i l f ill ti f i i d t i d i M tNominal range of oscillation frequencies is determined using Monte-Carlo analysis by including the tolerance of components and parameters of the CUT.

A device tolerance of 5% has been used for the frequency varying components R1, R2, R, C.

Process variation effects on the electrical characteristics (viz., Vth, µ0etc.) need to be considered while evaluating the fault tolerance. A lot tolerance 5% for Vth has been considered here.th

It can been simulated using SPICE command.MC |# runs| [Anal Type] |output variable| {list} {output | output specification}.

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Tolerance band of Oscillation FrequenciesTolerance band of Oscillation FrequenciesWith 5% tolerances for the componentsfor the components (R, C, R1, R2) and with 5% for Vth , the tolerance band oftolerance band of oscillation frequency was observed to be

[-3.7%, +4.1%]

and

Note: The tolerance band is calculated as follows:

f MAX = 910 kHz f MIN = 842 kHz

[Min, Max] = [(f MIN- f NAT)/ f NAT, (f MAX- f NAT)/ f NAT]

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Measured Oscillation Frequency

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% Deviation from Natural frequency

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ConclusionBICS f I t ti h b d i d f f ltBICS for IDDQ testing have been designed for fault detection.Circuits like op-amp, ADC and DAC have been designedCircuits like op amp, ADC and DAC have been designed as CUTs.Faults have been introduced using FITs.A new BICS for ΔIDDQ testing has been presented.Testing methods combining IDDQ, power supply current and oscillation current have been implementedand oscillation current have been implemented.

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Th kThank you