CMOS DESIGN RULES

• The physical mask layout of any circuit to be manufactured using a particular process.

• It must conform to a set of geometric constraints or rules, which are generally called layout design rules.

• The main objective of design rules is to achieve,a high overall yield and reliability while using the smallest possible silicon area.

These rules usually specify

Minimum allowable line widths such as metal and polysilicon interconnects.

Minimum feature dimensions.

Minimum allowable separations between two such features and many more…

Design rules which determine the dimensions of a minimum-

size transistor.

Design rules which determine the separation between the nMOS and the pMOS transistor of the CMOS inverter

The design rules are usually described in two ways:

1. Micron rules -

layout constraints such as minimum feature sizes and

minimum allowable feature separations are stated in terms of absolute

dimensions in micrometers (µm).

2. Lambda rules -

specify the layout constraints in terms of a single parameter (X) and thus allow

linear, proportional scaling of all geometrical constraints.

TECHNOLOGY SCALING

• Scaling is to either upscaling or downscaling the overall dimensions by constant scaling factor s > 1.

Types of scaling

1.Constant –field scaling (full scaling).

Effects of full scaling upon key device characteristics.

Full scaling of MOSFET dimensions, potentials, and doping densities.

2.constant voltage scaling -The power supply voltage and the terminal voltages remain unchanged.

Effects of constant-voltage scaling upon key device characteristics.

Constant-voltage scaling of MOSFET dimensions, potentials, and doping densities.

Design Rule Checker (DRC)

DRC is layout design tool used to check the dimensions of thedesign with thetechnology we are using.

Basically it compares our layout with standard design rule.

WHAT HAPPENS IF RULES ARE NOT FOLLOWED ??

• long polysilicon connections leads to large parasitic resistance and the parasitic capacitance of polysilicon lines.

• If a metal line width is made too small,it is possible for the line to break during

the fabrication process or afterwards resulting in an open circuit.

• If two lines are placed too close to each other in the layout, they may form an unwanted short circuit by merging during or after the fabrication process.

summary

• In general, the layout design rules significantly

increases the probability of fabricating a successful product with

high yield and reliability while using the smallest possible silicon area.