Chapter 4 flip flop for students

EE 202 : DIGITAL ELECTRONICS 1

Chapter 4:

FLIP FLOPS (Sequential Circuits)

By:Siti Sabariah Hj. SalihinELECTRICAL ENGINEERING DEPARTMENT

Programme Learning Outcomes, PLOProgramme Learning Outcomes, PLOProgramme Learning Outcomes, PLOProgramme Learning Outcomes, PLOUpon completion of the programme, graduates should be able to:

� PLO 1 :PLO 1 :PLO 1 :PLO 1 : Apply knowledge of mathematics, scince and engineering fundamentals to well defined electrical and electronic engineering procedures and practices

Course Learning Outcomes, CLOCourse Learning Outcomes, CLOCourse Learning Outcomes, CLOCourse Learning Outcomes, CLO� CLO 2 :CLO 2 :CLO 2 :CLO 2 : Simplify and design combinational and sequential logic

circuits by using the Boolean Algebra and the Karnaugh Maps.� CLO 3 :CLO 3 :CLO 3 :CLO 3 : Draw Logic Diagrams, truth tables and timing diagrams for

all common flip flops and use these to implement sequential logic circuits correctly.

CHAPTER 4 : FLIP FLOPSCHAPTER 4 : FLIP FLOPSCHAPTER 4 : FLIP FLOPSCHAPTER 4 : FLIP FLOPS

EE 202 : DIGITAL ELECTRONICS


Upon completion of this chapter, students should be able to:

1. Understand Types of Flip-Flop, Truth Tables, Symbols, Timing Diagram and its application in Logic Circuits.

2. Construct Types of Flip Flop using Types of Logic Gates by Drawing Symbols and Truth Tables, and Timing Diagram.

Learning outcomesLearning outcomesLearning outcomesLearning outcomes For Chapter 4:Flip Flops(Sequential Circuits)


Chapter's Summary

� Flip-FlopsFlip-FlopsFlip-FlopsFlip-Flops- Types- Types- Types- Types Of Flip Flops: SR Flip-Flop,

Clocked SR Flip-Flop, T Flip-Flop and JK Flip-Flop.

- Symbols- Symbols- Symbols- Symbols, Truth Tables and Timing.- T Flip-Flops and D Flip-Flops built built built built using JK Flip-Flops.


5

4.0 Introduction Sequential Circuits

� The output of circuit depends on the previous output and the present inputs.

� The inputs must follow a specific sequence to produce a required output.

� In order to follow a sequence of inputs the circuits must contain some form of memory to retain knowledge of those inputs, which have already occurred.

� This memory are obtained by feedback connections, which are made so that history of the previous inputs is maintained.

� Most sequential systems are based on a small number of simple sequential circuit elements known as Bistables or Flip Flops.


6

4.0 Flip Flop (Sequential Circuits)

�What is Flip flop?Answer:� In digital circuits, the flip-flopflip-flopflip-flopflip-flop, is a kind of bistablebistablebistablebistable multivibratormultivibratormultivibratormultivibrator. . . . � It is a Sequential Circuits / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0.


7

4.0 Introduction – Flip Flop

� They are 1 (HIGH) or 0 1 (HIGH) or 0 1 (HIGH) or 0 1 (HIGH) or 0 (LOW).(LOW).(LOW).(LOW).

� Whenever we refer to the statestatestatestate of flip flop, we refer to the state of its normal normal normal normal output (Q).(Q).(Q).(Q).

� More complicated Flip flopcomplicated Flip flopcomplicated Flip flopcomplicated Flip flop use a clockclockclockclock as the control input. These clocked flip-flops are used whenever the input and output signals must occur within a particular sequence.

Figure 4.0.1 : General Flip flop Figure 4.0.1 : General Flip flop Figure 4.0.1 : General Flip flop Figure 4.0.1 : General Flip flop symbol symbol symbol symbol

Inputs Q Normal output

Inverted Output

They have two stable conditions and can be switched from one to the other by appropriate inputs. These stable conditions are usually called the statesstatesstatesstates of the circuit.

Q


Introduction: Types Of Flip Flop

1. SR Flip Flop SR Flip Flop SR Flip Flop SR Flip Flop a.a.a.a. SR Flip Flop Active Low = NAND gatesSR Flip Flop Active Low = NAND gatesSR Flip Flop Active Low = NAND gatesSR Flip Flop Active Low = NAND gates b. SR Flip Flop Active High = NOR gates b. SR Flip Flop Active High = NOR gates b. SR Flip Flop Active High = NOR gates b. SR Flip Flop Active High = NOR gates2. 2. 2. 2. Clocked SR Flip Flop Clocked SR Flip Flop Clocked SR Flip Flop Clocked SR Flip Flop3. 3. 3. 3. JK Flip FlopJK Flip FlopJK Flip FlopJK Flip Flop4.4.4.4. JK Flip Flop With Preset And Clear JK Flip Flop With Preset And Clear JK Flip Flop With Preset And Clear JK Flip Flop With Preset And Clear5. 5. 5. 5. T Flip Flop T Flip Flop T Flip Flop T Flip Flop6. 6. 6. 6. D Flip Flop D Flip Flop D Flip Flop D Flip Flop

The Used of Flip Flop

� For Memory circuits� For Logic Control Devices� For Counter Devices� For Register Devices

10

4.1 SR Flip Flop

� The most basic Flip Flop is called SR Flip FlopSR Flip FlopSR Flip FlopSR Flip Flop. � The basic RS flip flop is an asynchronous device. � In asynchronous device, the outputs is immediately

changed anytime one or more of the inputs change just as in combinational logic circuits.

� It does not operate in step with a clock or timing.� These basic Flip Flop circuit can be constructed using

two NAND gates latch or two NOR gates latch.� SR Flip Flop Active LowSR Flip Flop Active LowSR Flip Flop Active LowSR Flip Flop Active Low = NAND gates� SR Flip Flop Active HighSR Flip Flop Active HighSR Flip Flop Active HighSR Flip Flop Active High = NOR gates


11

4.1 SR Flip Flop

� Figure 4.1.1: Figure 4.1.1: Figure 4.1.1: Figure 4.1.1: � SR Flip Flop logic SR Flip Flop logic SR Flip Flop logic SR Flip Flop logic

Symbol Symbol Symbol Symbol

� The SR Flip Flop has two inputs, SET (S) and RESET (R).

� The SR Flip Flop has two outputs, Q and ¯

� The Q output is considered the normal output and is the one most used.

� The other output ¯ is simply the compliment of output Q.

Q

Q


12

4.1 SR Flip Flop - NAND GATE LATCHNAND GATE LATCHNAND GATE LATCHNAND GATE LATCH

� NAND GATE LATCHNAND GATE LATCHNAND GATE LATCHNAND GATE LATCH

� Figure 4.1.2: SR NAND (Active Figure 4.1.2: SR NAND (Active Figure 4.1.2: SR NAND (Active Figure 4.1.2: SR NAND (Active LOW) Logic circuit.LOW) Logic circuit.LOW) Logic circuit.LOW) Logic circuit.

� The NAND gate version has two inputs, SET (S) and RESET (R).

� Two outputs, Q as normal output and ¯ as inverted output and feedback mechanism.

� The feedback mechanism is required to form a sequential circuit by connecting the output output output output of NAND-1NAND-1NAND-1NAND-1 to the inputinputinputinput of NAND-2NAND-2NAND-2NAND-2 and vice versa.

� The circuit outputs depends on the inputs and also on the outputs.

Q1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2


13


� Figure 4.1.3 Feedback Mechanism


14

4.1SR Flip Flop - NAND GATE LATCHNAND GATE LATCHNAND GATE LATCHNAND GATE LATCH

� Normal Resting State Figure 4.1.4.a

� Input S=1 , R=1 ,� This is the normal

resting state of the circuit and it has no effect of the output states.

� Output Q and ¯ will remain in whatever state they were in prior to the occurrence of this input condition.

� It works in HOLDHOLDHOLDHOLD mode of operation.

1

2

0

1

1

1

0

1

1

1

1

1

11 1

21

000

1

Q1

2


15


� Input, S = 0, R = 1S = 0, R = 1S = 0, R = 1S = 0, R = 1� This will set Q = 1.Q = 1.Q = 1.Q = 1.� It works in SETSETSETSET mode

operation.

� Figure 4.1.4.b

1

2

0

1

0 1

01


16


� Figure 4.1.4.c � Input S = 1, R = 0S = 1, R = 0S = 1, R = 0S = 1, R = 0� This will reset Q = 0.Q = 0.Q = 0.Q = 0.� It works in RESETRESETRESETRESET mode

operation.1

2

1

01

0

0

1


17


� Figure 4.1.4.d � This condition tries to set and reset the NAND gate latch at the same time.

� It produces Q = Q = Q = Q = ¯̄̄̄ = 1 = 1 = 1 = 1� This is unexpected condition,

since the two outputs should be inverses of each other.

� If the inputs are returned to 1 simultaneously, the output states are unpredictable.

� This input condition should not be used and when circuits are constructed, the design design design design should make this condition

S = R = 0 nevernevernevernever arises.It is called INVALID/PROHIBITEDINVALID/PROHIBITEDINVALID/PROHIBITEDINVALID/PROHIBITED

1

2

0

0 1

1

1

0

QQQQ


18


� From the description of the NAND gate latch operation, it shows that the SET and RESET inputs are active LOW.

� The SET input will set Q = 1 when SET is 0 (LOW).RESET input will reset Q = 0 when RESET is 0 (LOW)

� In the prohibited/INVALID state both outputs are 1. This condition is not used on the RS flip-flop. The set condition means setting the output Q to 1.

� Likewise, the reset condition means resetting (clearing) the output Q to 0. The last row shows the disabled, or hold, condition of the RS flip-flop. The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous states.

The flip-flop The flip-flop The flip-flop The flip-flop memorizesmemorizesmemorizesmemorizes the previous the previous the previous the previous condition. condition. condition. condition.

� Figure 4.1.5 : SR NAND gate Figure 4.1.5 : SR NAND gate Figure 4.1.5 : SR NAND gate Figure 4.1.5 : SR NAND gate latch Truth Table latch Truth Table latch Truth Table latch Truth Table

SSSS RRRR QQQQ ¯̄̄̄ STATUSSTATUSSTATUSSTATUS

0 0 1 1 INVALIDINVALIDINVALIDINVALID

0 1 1 0 SETSETSETSET

1 0 0 1 RESETRESETRESETRESET

1 1 Q ¯ HOLDHOLDHOLDHOLD(NoChange)(NoChange)(NoChange)(NoChange)

QQQQ

Q





1 1 Q ¯ HOLDHOLDHOLDHOLD(NoChange)(NoChange)(NoChange)(NoChange)


19

4.1 SR NAND Flip Flop-Waveforms

Exercise 4.1.1:Exercise 4.1.1:Exercise 4.1.1:Exercise 4.1.1:Determine the output of NAND gate latch which Q initially 1Q initially 1Q initially 1Q initially 1 for the given input waveforms.

SRQ

¯

Example 4.1.1:Example 4.1.1:Example 4.1.1:Example 4.1.1: Determine the output of NAND gate latch which Q initialy 0 for the given input waveform.

S

R

Q

¯QQ


20

4.1 SR Flip Flop - NOR GATE LATCHNOR GATE LATCHNOR GATE LATCHNOR GATE LATCH

� NOR GATE LATCHNOR GATE LATCHNOR GATE LATCHNOR GATE LATCH

� Figure 4.1.6: SR NOR SR NOR SR NOR SR NOR (Active HIGH) Logic circuit (Active HIGH) Logic circuit (Active HIGH) Logic circuit (Active HIGH) Logic circuit

� The latch circuit can also be constructed using two NOR gates latch.

� The construction is similar to the NAND latch except that the normal output QQQQ and inverted output ¯̄̄̄ have reversed positions.

QQQQ


21


The analysis of a SR FLIP FLOP SR FLIP FLOP SR FLIP FLOP SR FLIP FLOP NOR :NOR :NOR :NOR :

**** S = 0, R = 0; S = 0, R = 0; S = 0, R = 0; S = 0, R = 0; This is the normal resting state of the circuit and it has no effect of the output states.Q and Q and Q and Q and ¯̄̄̄ will remain in whatever state they were in prior to the occurrence of this input condition. It works in HOLD (no change)HOLD (no change)HOLD (no change)HOLD (no change) mode operation.

• S = 0, R = 1;S = 0, R = 1;S = 0, R = 1;S = 0, R = 1; This will reset Q to Q to Q to Q to 0000, it works in RESETRESETRESETRESET mode operation.

SR FLIP FLOP NOR SR FLIP FLOP NOR SR FLIP FLOP NOR SR FLIP FLOP NOR (Active HIGH) Logic circuit (Active HIGH) Logic circuit (Active HIGH) Logic circuit (Active HIGH) Logic circuit

QQQQ


22


� S = 1, R = 0;S = 1, R = 0;S = 1, R = 0;S = 1, R = 0; This will set Q to 1Q to 1Q to 1Q to 1, it works in SET SET SET SET mode operation.� S = 1, R = 1;S = 1, R = 1;S = 1, R = 1;S = 1, R = 1; This condition tries to set and reset the NOR gate

latch at the same time, and it produces Q = Q = Q = Q = ¯̄̄̄ = 0. = 0. = 0. = 0. This is an unexpected condition and are not used.

Since the two outputs should be inverse of each other. If the inputsare returned to 1 simultaneously, the output states are unpredictable. This input condition should not be used and when circuits are constructed, the design should make this condition SET=RESET = 1 never arises.

QQQQ


23


� From the description of the NOR gate latch operation, it shows that the SET and RESET inputs are Active HIGH.

� The SET input will set Q = 1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1 (HIGH).

� Figure 4.1.7 : SR NOR gate latch : SR NOR gate latch : SR NOR gate latch : SR NOR gate latch Truth Table Truth Table Truth Table Truth Table


0 0 HOLDHOLDHOLDHOLD(NoChange)(NoChange)(NoChange)(NoChange)




QQQQ QQQQ

QQQQ____


24

4.1 SR NOR Flip Flop -WaveformsWaveformsWaveformsWaveforms

� Example 4.1.2Example 4.1.2Example 4.1.2Example 4.1.2: Determine the output of NOR gate latch which Q initially 0Q initially 0Q initially 0Q initially 0 for the given input waveforms.

S S S S

R R R R

QQQQ

¯̄̄̄

� Exercise 4.1.2Exercise 4.1.2Exercise 4.1.2Exercise 4.1.2 : Determine the output of NOR gate latch which Q initially 1 for the given input waveforms.

S S S S

R R R R

Q Q Q Q

¯̄̄̄QQQQ QQQQ


25

4.2 The CLOCK� In synchronous device, the exact times at

which any output can change states are controlled by a signal commonly called the clock.

� The clock signal is generally a rectangular pulse train or a square wave as shown in figure 4.9.

� The clock is distributed to all parts of the system, and most of the system outputs can change state only when the clock makes a transition.


26

4.2 The CLOCK� When the clock changes from a LOW state to a HIGH

state, this is called the positive-going transition (PGT) or positive edge triggered.

� When the clock changes from a HIGH state to a LOW state, it is called negative going transition (NGT) or negative edge triggered.

Figure 4.2.1: Clock Pulse-TrainFigure 4.2.1: Clock Pulse-TrainFigure 4.2.1: Clock Pulse-TrainFigure 4.2.1: Clock Pulse-Train

(a) Positive going transition(a) Positive going transition(a) Positive going transition(a) Positive going transition

(b) Negative going transition(b) Negative going transition(b) Negative going transition(b) Negative going transition

Enable

Disable


27

4.2 Clocked SR Flip Flop

� Additional clock input is added to change the SR flip-flop from an element used in asynchronous sequential circuits to one, which can be used in synchronous circuits.

� The clocked SR flip flop logic symbol that is triggered by the PGT is shown in Figure Figure Figure Figure 4.2.24.2.24.2.24.2.2

� Its means that the flip flop can change the output states only when clock signal makes a transition from LOW to HIGH.

� Figure 4.2.2 : PGT Clocked SR Flip PGT Clocked SR Flip PGT Clocked SR Flip PGT Clocked SR Flip flop symbolflop symbolflop symbolflop symbol


28

4.2 Clocked RS Flip Flop

Figure 4.2.3: Truth Table for Truth Table for Truth Table for Truth Table for clocked SR Flip Flopclocked SR Flip Flopclocked SR Flip Flopclocked SR Flip Flop

clock SSSS RRRR QQQQ ¯̄̄̄ STATUSSTATUSSTATUSSTATUS

0 0 Q Q HOLDHOLDHOLDHOLD(NoChange)(NoChange)(NoChange)(NoChange)




•The Truth Table Truth Table Truth Table Truth Table in figure 4.2.3 shows how the flip flop output will respond to the PGT at the clocked input for the various combinations of SR inputs and output.

• The up arrow symbol indicates PGT.PGT.PGT.PGT.

QQQQ____


29

� Example 4.2.1:Example 4.2.1:Example 4.2.1:Example 4.2.1: Determine the output of PGTPGTPGTPGT clocked SR flip flop which Q initially 0Q initially 0Q initially 0Q initially 0 for the given input waveforms

CpCpCpCp

S S S S

RRRR

QQQQ

¯̄̄̄

� Exercise 4.2.1:Exercise 4.2.1:Exercise 4.2.1:Exercise 4.2.1: Determine the output of PGT PGT PGT PGT clocked SR flip flop which Q initially 1Q initially 1Q initially 1Q initially 1 for the given input waveforms.

Cp

S

R

Q

¯


QQQQ QQQQ


30


� Figure 4.2.4 : NGT Clocked NGT Clocked NGT Clocked NGT Clocked SR Flip flop symbolSR Flip flop symbolSR Flip flop symbolSR Flip flop symbol

� The clocked SR Flip Flop logic symbol that is triggered by the NGT is shown in Figure 4.2.4Figure 4.2.4Figure 4.2.4Figure 4.2.4

� It means that the Flip flop can change the output states only when clocked signal makes a transition from HIGH to LOWHIGH to LOWHIGH to LOWHIGH to LOW.


31


� Figure 4.2.5: CLOCKED SR CLOCKED SR CLOCKED SR CLOCKED SR FLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUIT


32


� Figure 4.2.6: CLOCKED SR CLOCKED SR CLOCKED SR CLOCKED SR FLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUITFLIP FLOP LOGIC CIRCUIT

� If used NOR GateNOR GateNOR GateNOR Gate, must used AND AND AND AND Gate in front.


33


� Example 4.2.2Example 4.2.2Example 4.2.2Example 4.2.2: Determine the output of NGTNGTNGTNGT clocked SR flip flop which Q initially 0Q initially 0Q initially 0Q initially 0 for the given input waveforms

Cp

S

R

Q

¯

� Exercise 4.2.2Exercise 4.2.2Exercise 4.2.2Exercise 4.2.2: Determine the output of NGT NGT NGT NGT clocked SR flip flop which Q initially 1Q initially 1Q initially 1Q initially 1 for the given input waveforms.

CpCpCpCp

S S S S

R R R R

Q Q Q Q

¯̄̄̄QQQQ QQQQ


34

4.3 JK Flip Flop - Symbol

� Another types of Flip flop is JK flip flop.

� It differs from the RS flip flops when J=K=1 condition is not indeterminate but it is defined to give a very useful changeover (toggle) action.

� Toggle means that QQQQ and ¯ will switch to their opposite states.

� The JK Flip flop has clock input Cp and two control inputs J and K.

� Operation of Jk Flip Flop is completely described by truth table in Figure 4.3.3.

� Figure 4.3.1 : PGT JK Flip PGT JK Flip PGT JK Flip PGT JK Flip flop symbolflop symbolflop symbolflop symbol

� Figure 4.3.2 : NGT JK Flip NGT JK Flip NGT JK Flip NGT JK Flip flop symbolflop symbolflop symbolflop symbol

Q Q Q Q


35

4.3 JK Flip Flop – Truth Table And Logic Circuit

Figure 4.3.3: Truth Table for JK Truth Table for JK Truth Table for JK Truth Table for JK Flip FlopFlip FlopFlip FlopFlip Flop

� Figure 4.3.4: JK FLIP FLOP JK FLIP FLOP JK FLIP FLOP JK FLIP FLOP LOGIC CIRCUITLOGIC CIRCUITLOGIC CIRCUITLOGIC CIRCUIT

clock JJJJ KKKK QQQQ ¯̄̄̄ STATUSSTATUSSTATUSSTATUS

0 0 HOLDHOLDHOLDHOLD(No Change)(No Change)(No Change)(No Change)



1 1 ToggleToggleToggleToggle

QQQQ

QQQQ____QQQQ

QQQQ QQQQ____


36

4.3 JK Flip Flop - waveforms

Example 4.3.1Example 4.3.1Example 4.3.1Example 4.3.1 : Determine the output of PGT clocked JK flip flop for the given input waveforms which the Q initially 0.

JJJJ

ClkClkClkClk

KKKK

QQQQ


37

4.3 JK Flip Flop - waveforms

Exercise 4.3.1Exercise 4.3.1Exercise 4.3.1Exercise 4.3.1:Determine the output of NGTNGTNGTNGT clocked JK flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

Exercise 4.3.2Exercise 4.3.2Exercise 4.3.2Exercise 4.3.2:Determine the output of PGTPGTPGTPGT clocked JK flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

JJJJ

KKKK

QQQQ

CpCpCpCp

¯̄̄̄QQQQ

CpCpCpCp CpCpCpCp

KKKKJJJJ

QQQQ

QQQQ

¯̄̄̄


38

4.4 JK Flip Flop with Asynchronous Input

� The J and K inputs are called synchronous inputs since they only influence the state of the flip flop when the clocked pulse is present.

� This flip flop can also have other inputs called Preset (or SET) and clear that can be used for setting the flip flop to 1 or resetting it to 0 by applying the appropriate signal to the Preset and Clear inputs.

� These inputs can change the state of the flip flop regardless of synchronous inputs or the clock.


39

4.4 JK Flip Flop with Preset and Clear

Figure 4.4.1 :Figure 4.4.1 :Figure 4.4.1 :Figure 4.4.1 : Symbol and Truth Table


40


� Example 4.4.2Example 4.4.2Example 4.4.2Example 4.4.2 : The output of clocked JK flip flop which output initially 0initially 0initially 0initially 0 for the given input waveforms.

Cp Cp Cp Cp

PresetPresetPresetPreset

ClearClearClearClear

JJJJ

KKKK

QQQQ

QQQQ


41


� Exercise 4.4.3Exercise 4.4.3Exercise 4.4.3Exercise 4.4.3 : The output of clocked JK flip flop which output initially 0initially 0initially 0initially 0 for the given input waveforms.

Cp

Preset

J

K

Clear

Q


42

4.5 T Flip Flop - Symbol

� The T flip flop has only the Toggle and Hold Operation.

� If Toggle mode operation. The output will toggle from 1 to 0 or vice versa.

� Figure 4.5.1:Figure 4.5.1:Figure 4.5.1:Figure 4.5.1: Symbol for T Flip Flop

T clockclockclockclock Q statusstatusstatusstatus

0 Q Q HOLD

1 Q Q TOGOL

Q

Figure 4.5.2Figure 4.5.2Figure 4.5.2Figure 4.5.2 :Truth Table for T Flip Flop

CPT


43

4.5 T Flip Flop – Logic Circuit

Cp

TTTTTTTT

Logic circuit TTTT Flip flop using NORNORNORNOR gate

Logic circuit TTTT Flip flop using NANDNANDNANDNAND gate

�Figure 4.5.3:Figure 4.5.3:Figure 4.5.3:Figure 4.5.3: Logic circuit for T Flip Flop


44

4.5 T Flip Flop – Waveforms

Example 4.5.1Example 4.5.1Example 4.5.1Example 4.5.1 : Determine the output of PGT PGT PGT PGT TTTT flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

TTTT

ClkClkClkClk

QQQQ

QQQQ


45

4.5 T Flip Flop – Wave forms

Exercise 4.5.1Exercise 4.5.1Exercise 4.5.1Exercise 4.5.1 : Determine the output of PGTPGTPGTPGT TTTT flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

Exercise 4.5.2Exercise 4.5.2Exercise 4.5.2Exercise 4.5.2 : Determine the output of NGTNGTNGTNGT TTTT flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

CpCpCpCpCpCpCpCp

QQQQ

TTTT

QQQQ

QQQQ

TTTT

QQQQ


46

4.6 D Flip Flop

� Also Known as Data Flip flop� Can be constructed from RS

Flip Flop or JK Flip flop by addition of an inverter.

� Inverter is connected so that the R input is always the inverse of S (or J input is always complementary of K).

� The D flip flop will act as a storage element for a single binary digit (Bit).

� Figure 4.6.1 :Figure 4.6.1 :Figure 4.6.1 :Figure 4.6.1 :� D Flip flop symbolD Flip flop symbolD Flip flop symbolD Flip flop symbol


47

4.6 D Flip Flop - Symbol

� PGT � NGT

DDDD

Clk Clk Clk Clk

QQQQ

QQQQ

DDDDFlip FlopFlip FlopFlip FlopFlip Flop

Positive EdgePositive EdgePositive EdgePositive Edge

DDDD

Clk Clk Clk Clk

QQQQ

QQQQ

DDDDFlip FlopFlip FlopFlip FlopFlip Flop

Negative EdgeNegative EdgeNegative EdgeNegative Edge

Figure 4.6.2 : Figure 4.6.2 : Figure 4.6.2 : Figure 4.6.2 : D Flip flop symbol using JK Flip Flop / SR Flip Flop


48

4.6 D Flip Flop- Logic circuit-Truth Table

� Figure 4.6.3:Figure 4.6.3:Figure 4.6.3:Figure 4.6.3: Logic circuit for D Flip Flop

� Figure 4.6.4:Figure 4.6.4:Figure 4.6.4:Figure 4.6.4: Truth Table for D Flip Flop

D clockclockclockclock Q ¯ statusstatusstatusstatus

0 0 1 RESETRESETRESETRESET

1 1 0 SET

Q

Cp


49

4.6 D Flip Flop – Waveforms

Example 4.6.1Example 4.6.1Example 4.6.1Example 4.6.1 : Determine the output of PGTPGTPGTPGT DDDD flip flop for the given input waveforms which the Q initially 0.Q initially 0.Q initially 0.Q initially 0.

Cp Cp Cp Cp

D D D D

� Exercise 4.6.1 Exercise 4.6.1 Exercise 4.6.1 Exercise 4.6.1 Determine the output of NGT DNGT DNGT DNGT D flip flop for the given input waveforms, which output Q initially 0.

CpCpCpCp

D D D D

QQQQ

QQQQ

QQQQ

QQQQ


50

4.7 T Flip Flops and D Flip Flops can be Built using JK Flip Flop

� The JK flip flop is considered as a universal flip flop.

� A combination of Jk flip flop and an inverter can construct a D Flip Flop as shown in Figure 4.18

� It also can construct T Flip Flop by combine both J and K inputs with HIGH level input as shown in Figure 4.19

� Figure 4.7.1 : D Flip flop D Flip flop D Flip flop D Flip flop symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR Flip FlopFlip FlopFlip FlopFlip Flop

� Figure 4.7.2 : T Flip flop T Flip flop T Flip flop T Flip flop symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR symbol using JK Flip Flop / SR Flip FlopFlip FlopFlip FlopFlip Flop

T


1. "Digital Systems Principles And Application" Sixth Editon, Ronald J. Tocci.

2. "Digital Systems Fundamentals" P.W Chandana Prasad, Lau Siong Hoe, Dr. Ashutosh Kumar Singh, Muhammad Suryanata.

ReferencesReferencesReferencesReferences

Download Tutorials EE202 @ CIDOSDownload Tutorials EE202 @ CIDOSDownload Tutorials EE202 @ CIDOSDownload Tutorials EE202 @ CIDOShttp://www.cidos.edu.myhttp://www.cidos.edu.myhttp://www.cidos.edu.myhttp://www.cidos.edu.my

The END…….

Review Chapter Flip flop by Lecturer

52EE 202 : DIGITAL ELECTRONICS

Technology

Chapter 4 flip flop for students