Basics of vlsi

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V L S IWELCOME

Lavesh KumathHead, R & D (VLSI Division )Scientech Technologies Pvt. Ltd., [email protected]

mailto:[email protected]


THE ART OF VLSIBasics of VLSI


Semi conductor

Diodes

Transistors

FET

JFET

N Chan P Chan

BJT – TTL,RTL, ECL

MOSFET

N MOS P MOS CMOS

Gates

ICs

endless Journey……

Power

Area Speed

Density

Functionality FeaturesSSI MSI LSI VLSI

Gates

ICs

SSI MSI LSI

DTL


TTL Logic

Design Specification

Truth Table

Boolean Expression

AvailableInventory

Cost and performancerequirement

Logic minimizationand multilevel

logic optimization

Implementation

General Design Flow….


Digital Design Process

A B C D X

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Logic 2 or >2 I/P = 1 then O/P 1

1. Design Specifications 2. Truth Table

0 0 1 0

0 1 1 1

1 1 1 1

0 1 1 1

/CD 00 01 11 10AB

00

01

11

10

Boolean Eq. -> X = AB + CD + BD + BC + AD + AC OR X’ = A’B’C’ + A’B’D’ + A’C’D’ + B’C’D’

3. Reduce Expression

A B C D

O/P = X


Digital Design Process1. Design Specifications

2. Truth Table

3. Reduction using Boolean or K Map

Boolean Eq. -> X = AB + CD + BD + BC + AD + AC --> 2 - 7408, 3 - 7432, 3 level of logic 1 - 7474 for synchronization

4. Minimize of Device or No. of Level i.e. Cost Vs Performance (Min Prop. Delay)

5. Examine Available Inventory

6. Eqn Re-written in NAND-NAND implementation

Few Device and Few logic i.e. Less Cost and Better Performance

Boolean Eq. -> X = {(AB)’. (CD)’ . (BD)’ .(BC)’. (AD)’ .(AC)’ }’ --> 2 - 7400, 1 - 7430, 2 level of logic 1 - 7474 for synchronization 1

2


Basics of VLSI ………..

• VLSI Introduction

• History of VLSI.

• Why VLSI …. ?

• VLSI Design Styles

• VLSI Design Flows

• VLSI Design Approaches

• Xilinx Vs Altera


VERY LARGE SCALE INTEGRATION

“ Is the art of integrating millions of transistors on a Silicon Chip ”


“ A device called a transistor, which has several applicationsIn radio where a vacuum tube ordinarily is employed, was

demonstrated for the first time at Bell Telephone Laboratories, 463 West Street, where it was invented.”

23 December 1947

The First Transistor

First point contact transistor (germanium), 1947John Bardeen and Walter Brattain

Bell Laboratories

History of IC Design


- Evolution of ICs -

Vacuum tubes

Transistors

Gates

ICs

?High Performance

High Reliability

High complexity or small Area

High applicability

Low Power Dissipation

Low power consumption

Low Cost

Fast Design time

Simple Design Process

Integrated Circuits

IC is a collection of Electronic Circuits made by simultaneously forming individual Transistors, Diodes and Resistors on a small chip of Semiconductor material, typically

silicon that are interconnected to one another with a metal, such as aluminum, deposited on the chip surface.


The Progressive Trend of IC Technology

Integration Level Number of TransistorsYear

SSI - Individual Gates

MSI - Counter, Shift Reg.

LSI - Small Logic Function

VLSI - Large Logic Function

1950s

1960s

1970s

1980s

1990s

2000s

Less than 10^2

10^2 – 10^3

10^3 – 10^5

10^5 – 10^7

10^7 – 10^9

Over 10^9


Evolution in IC Complexity


Moore’s Law

http://www.intel.com/technology/silicon/mooreslaw/

In 1965, Intel co-founder Gordon Moore

saw the future. His prediction, now popularly

known as Moore's Law, states that

“The number of transistors on a chip doubles about every two years”

Transistor Count – Number of Transistor doubles every 2-3 Yrs

Clock Frequency – Clock Frequency doubles every 2.168 Yrs

Other Trends-

Features Size – Gate Length is divided by 2 every 5.43 Yrs

http://www.intel.com/technology/silicon/mooreslaw/


VLSI Technology - CMOS Transistors

Key feature:transistor length L

p+ p+

n substrate

channel

Source Drain

p transistor

G

S

D

SB

Polysilicon GateSiO2Insulator L

W

G

substrate connectedto VDD

Polysilicon GateSiO2Insulator

n+ n+

p substrate

channel

Source Drain

n transistor

G

S

D

SB

LW

G

S

D

substrate connectedto GND

2002: L=130nm2003: L=90nm2006: L=65nm


2002 and beyond ?

Semiconductor Industry Association (SIA) Road Map, 1998 Update1999 2002 2014

Technology (nm) 180 130 35Wafer diameter (mm) 300 300 450Memory-samples (bits) 1G 4G 1TTransistors/cm2 (P) 6.2M 18M 390MWiring levels (maximum) 6-7 7 10Clock, local (MHz) 1250 2100 10000Chip size: DRAM (mm2) 400 560 2240Chip size: P (mm2) 340 430 901Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42Maximum Power (W) 90 130 183Number of pins (P) 700 957 3350

IEEE Spectrum, July 1999

Special report: “The 100-million transistor IC”

These scaling trends will allow the electronics market to growth at 15% / year


Power & Clock Frequencies

Power Consumption, Clock frequency, Supply Voltage are related as follows :-

Capacitance Supply Voltage Clock Frequency


Why VLSI Design ?

• Large Scale Integration -

Size ….. <<<

Speed …. >>>

Power …. <<<

• Integration reduce manufacturing costs (almost) no manual assembly

• Money Vs Performance


VLSI Design Styles

Integrated Circuits

Full-CustomASICs

Semi-CustomASICs

UserProgrammable

PLD FPGA

SPLDPLAPAL LUT(Look-Up Table)

MUXGates

System-OnCHIP

CPLD

1 2 3 4


VLSI Design Styles

1. Programmable Logic (PLD, FPGA)

2. Application-Specific Integrated Circuit (ASIC)

3. Full Custom

4. System-on-Chip


VLSI Design Styles

Integrated Circuits

Full-CustomASICs

Semi-CustomASICs

UserProgrammable

FPGA

LUT(Look-Up Table)

MUXGates

System-OnCHIP

PLD

SPLDPLAPAL CPLD

1 2 34


1. Programmable Logic (PLDs, FPGAs)

• Pre-manufactured components with programmable interconnect

• CAD tools greatly reduce design effort

• Low Design Cost

• Low NRE Cost

• High Unit Cost

• Lower Performance as compared to ASIC better than General digital design


Logic Circuits

Standard Logic Circuits Programmable Logic Circuits• Realize single function or set of

functions • No possibility of changing.• More Debugging Time• More Interconnections and I/Os• High Standby and Switching current• No Design Security• Not Flexible• No Tools for Automation• More NRE & Time to Market Single Change require – redesign

• Possibility of realizing various functions

• Re-configurable• Less Debugging Time• Fewer total I/Os & Switching O/P- • Lower Standby & Switching Currents• Design Security • Flexibility …….. Greatest Advantage• Automation is Possible• Less NRE & Less Time to market only reprogramming is required

…… FPLD


• PLA - Programmable Logic Arrays• PAL - Programmable Array Logic• CPLD - Complex Programmable Logic Devices• FPGA - Field Programmable Gate Arrays

PLD

FPLD Representatives


What is a CPLD ?

Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLD.

CPLD uses less board space, improve reliability, and reduce cost.

CPLD contains multiple logic block, which communicate with one another using Signals routed via a programmable interconnect.

Easily Routed.

CPLDs are great at handling wide and complex gating at blistering speeds e.g. 5ns which is equivalent to 200MHz.


CPLD Architecture


CPLD Architecture

Complex Programmable Logic Devices


Why use a CPLD ?

Ease of Design

Lower Development Costs

More Product Revenue

Reduced Board Area

Reconfigurable

Flexible


Evolution of PLD: FPGA

• Difficult extending CPLDs architectures to higher densities - a different approach is needed

• FPGAs comprise an array of uncommited circuit elements, called logic blocks, and interconnect resources

• FPGA configuration is performed through programming by the end user.Xilinx FPGA

Configuration

contains a set of basic functions

(gates, FFs, memory cells)

www.ScientechWorld.com 29

General FPGA Architecture• Field Programmable Gate Array


FPGAs -- Pros

• Reasonably Cheap at low volume– Good for low-volume parts, more expensive than IC for high-volume parts– Can migrate from SRAM based to fuse based when volume ramps up

• Short Design Cycle (~1sec programming time)• Reprogrammable

– Can download bug fix into units you’ve already shipped• Large capacity (100 million gates or so .….• More flexible than PLDs -- can have internal state• More compact than MSI/SSI


FPGA’s -- Cons

• Lower capacity, speed and higher power consumption than building an ASIC– Sub-optimal mapping of logic into CLB’s – often 60% utilization

– Much lower clock frequency

– Less dense layout and placement and slower operation due to programmability

• Overhead of configurable interconnect and logic blocks

• PLDs may be faster than FPGA for designs they can handle

• Need sophisticated tools to map design to FPGA


Key Factors For Comparing FPGAs

• Logic density

• Clock management

• On-chip memory

• DSP capabilities

• I/O compatibility

• Software support & other design services


Programmable Logic (PLDs, FPGAs)• Pre-manufactured components with programmable interconnect• CAD tools greatly reduce design effort• Low Design Cost / Low NRE Cost / High Unit Cost• Lower Performance

Medium Type Design, Combinational CLB – LUT, MUX, FF, I/Os, PI, DLL, Sequential


ADVANTAGES OF PROGRAMMABLE LOGICS

• Save Valuable Board Space• Power Requirement is low• Increases Performance• Design Security• Lower Standby and Switching Current • Integration increases Design Reliability• I/Os Delay Reduces• Flexibility • No NRC Cost• Low Time to market• Process Automation• High Density ……… or Complex Design


How to Cope with Complexity ?Electronic Design Automation (EDA)• Computer Aided Design (CAD) …. Front - end• Computer Aided Engineering (CAE) …. Back - end

Simulation – H-Spice (Synopsis), Spector (Cadance), Spector RF, H-Sim (Synopsis for Digital), DA (Design Architect Mentor), Co-Sim (Synopsis for Mixed), FineSim SPICE, Fine Wave (Megma)

Synthesis & Implementation - DC (Synopsis), ISE (Xilinx), Quartus (Altera), Blast – Integrated RTL-to-GDSII Flow (Megma)

Timing Analysis & Verification – Prime Time, Formality – (Synopsis), DRC & LVS (Magma), Modelsim – Mentor,

Physical Design – Astro, Layout – Vertuoso (Cadance), Magic, L-Edit


Design Entry

Synthesis

Implementation

Bit Stream

Configurable Logic

Configurable Switch Matrix

Configuration Memory

Software PLD Chip

VolatileNon-volatile

TransistorSwitch Muxes

LUT’s or GatesFlip-flop

User Constraint file

Gate Level circuit

Device Type, Constraints Floor Planning

Device type ,

Constraint

VHDL or Verilog code

Device independent

Download cable

General Tool Flow for PLDs


VLSI Design Styles

Integrated Circuits

Full-CustomASICs

Semi-CustomASICs

UserProgrammable

PLDFPGA

SPLDPLAPALLUT(Look-Up Table)

MUXGates

System-OnCHIP

CPLD

1 2 34


2. Application-Specific Integrated Circuit (ASIC)

• Constrained design using pre-designed (and sometimes pre-manufactured) components

• Also called semi-custom design

• CAD tools greatly reduce design effort

• Low Design Cost / High NRE Cost / Med. Unit Cost

• Medium Performance


• Designs must be sent for expensive and time consuming fabrication in semiconductor foundry

• Bought off the shelf and reconfigured by designers themselves

Two competing implementation approaches

ASICApplication SpecificIntegrated Circuit

FPGAField Programmable

Gate Array

• Designed all the way from behavioral description to physical layout

• No physical layout design; design ends with a bitstream used to configure a device


Balance ………. FPGAs

Off-the-shelf

Low development cost

Short time to market

Re-configurability

High performance

ASICs

Low power

Low cost inhigh volumes


ASICASIC == AApplicationpplication SSpecificpecific IIntegratedntegrated CCircuitsircuits tailor-made on demand for specific applicationstailor-made on demand for specific applications

FPGAFPGA == FFieldield PProgrammablerogrammable GGateate AArrayrray flexibility of software + speed of hardware flexibility of software + speed of hardware designdesign

Which way to Go


3. Full Custom Design

• Each circuit element carefully “handcrafted”• NO use of any Library.• Huge design effort.• High Design & NRE Costs• High Performance• Typically used for high-volume applications• Design Productivity is Very Low


4. System-on-a-chip (SOC)

• Idea: combine several large blocks– Predesigned custom cores

(e.g., microcontroller) - “intellectual property” (IP)

– ASIC logic for special-purpose hardware

– Programmable Logic (PLD, FPGA)

– Analog

• Open issues– Keeping design cost low– Verifying correctness of

design


VLSI Design Flow & Tools


Front-end & Back-end

Front-end Back-end

• Logic design (RTL)

• Simulation

• Synthesis

• Implementation

• Floorplanning

• Placement

• Routing

• GDSII (final Output, Foundary)

Verification


• Microelectronic system

• ASICs

• System partitioning

• ASIC floorplanning

• Placement

• Routing

• A City

• Buildings

• City planner

• Architect

• Builder

• Electrician

Physical design vs. Building a City


Programmable Logic Vendors

Xilinx - Xilinx Foundation Series.

Altera - Max Plus – II

Lattice - ISP Expert Compiler

Actel - Actel’s Designer Series FPGA Development System

Lucent - ORCA Foundry Development System

Cypress - Warp2

Atmel - FPGA Integrated Development System ( IDS )

QuickLogic - QuickWorks

Gatefield - ASIC master


XILINX Vs ALTRA Design Flow, Tools and Files

• Key players: Xilinx, Altera, Lattice, Actel• PLD market estimated at $57 billion and rapidly growing• The goal is to expand the market:

– by lowering per-unit cost to attack the low-end market– by increasing speed capabilities to attack the high-end market

PLD market sharePLD market share


• Virtex and Stratix families are direct opponents, as are Spartan and CycloneVirtex and Stratix families are direct opponents, as are Spartan and Cyclone

XILINX Vs ALETRA

Altera Xilinx

Cyclone Spartan

Stratix Virtex

Stratix Kintex

Max10 Artix


FPGA Design Flow – Xilinx - ISEDesign Entry

Design Synthesis

Design Implementation

Download to Device

Functional Simulation

Static Timing Analysis

Timing Simulation

In Circuit Verification

Design Verification

*Translate

*Mapping

*P & R

*Fitting

*Bit stream Generation

•Schematic editor•HDL (.v or .vhd)

Text – (EDIF, XNF) XST + GUI = NGC

UCF

Net list + Constraints = NGD

NCD – Native Circuit Description

VM6 -------- CPLD

.BIT or .JED

Library


Xilinx Devices at a Glance

FPGAs

CPLDs

Vertex

Spartan

Cool Runner

XC9500

XC9500, 5V, 36 to 288 MacrocellsLow Cost

XC9500XL, 3.3V, 36 to 288 Macrocells

XC9500XV, 2.5V, 36 to 288 Macrocells

XCR3000XL, 3.3V, 36 to 512 Macrocells

XC2Cxxx, 1.8V, 32 to 512 MacrocellsLow Power, High Speed, Low Cost

Spartan, 5V, 5000 to 40000 Max System Gates

Spartan II E, 1.8V, 50000 to 300000 Max System Gates

Vertex, 2.5V, 50000 to 1 Mil. Max System Gates

VertexII, 1.5V, 40000 to 10 Mil. Max System Gates

VertexE, 1.8V, 50000 to 3.2 Mil. Max System Gates

Spartan II , 2.5V, 15000 to 200000 Max System Gates

Spartan XL, 3.3V, 5000 to 40000 Max System GatesLow Cost

Feature Rich, High Density


Altera Devices at a Glance

• Programmable Logic Families

– High & Medium Density FPGAs• Stratix™ II, Stratix, APEX™ II,

APEX 20K, & FLEX® 10K– Low-Cost FPGAs

• Cyclone™ & ACEX® 1K

– FPGAs with Clock Data Recovery• Stratix GX & Mercury™

– CPLDs• MAX® 7000 & MAX 3000

– Embedded Processor Solutions• Nios™, ExcaliburT™


TTL Logic


Truth Table

Boolean Expression

AvailableInventory

Cost and performancerequirement

Logic minimizationand multilevel

logic optimization

Implementation


Design Description

Design Software

Fuse Map

Programmable Logic

Compare Design Process ….

Device


The Goal of IC Designer

Meet the market requirement

Satisfying the customers needs

- Beating the competition

- Increasing the functionality

- Reducing the cost

Achieved by

- using the next generation Silicon Technologies

- new design concepts & tools

- high level integration
