FM 1990-2009 AN 03

D W S & D W V

M O D E L I N G A N D S I M U L A T I O N O F

S E M I C U S T O M C M O S C H I P S

One of the problems in the

development of new semicustom

CMOS arrays and families is the on

chip power distribution. In fact, the

switching noise caused by the

simultaneous activation of a large

number of output buffers at the

same time (for example an n-bits

bus) can be dangerous for the core

logic timing. We present an

approach to the problem based on

transmission line modeling (TLM).

This methodology shows good

results in the current technology,

where the transition time is

comparable with the propagation

delay of the interconnection on

chip. The results show the impact

of TLM methodology about noise

margin analysis and propagation

delay evaluation. Also slow-wave

propagation and package effects are

considered.

INTRODUCTION

The increasing complexity of the

new semicustom CMOS families

and the increasing speed of the

current submicron technology are

emphasizing switching noise

problems. In fact, CMOS circuitry

produces more noise than the

bipolar equivalent. Taking in

account these issues is becoming

more and more important for the

development of new families, for

power and ground topology and I/O

buffers and packages compatibility

evaluation. Because the faster

transition times are now around

200ps, and the propagation delay on

silicon (considering slow-wave

effects) is about 150ps/cm, the

problem has to be approached using

transmission line modeling. The

slow-wave effect is due to a

propagation mode typical of MIS

(Metal Insulator Semiconductor)

structures. This effect causes 2-3

times increase in the delay time.

Moreover, also the rise time

increases due to the dispersion of

the frequency because the slow-

wave factor is not linear with

frequency.

The simulations reported in this

document refer to the model shown

in Fig. 1, and have been performed

using the simulator DWS and his

graphic environment DWV. All the

waveforms displayed are referred to

an external ground node. The cells

described in the device are modeled

at transistor level by means of DWS

macro models (Fig. 2).

The static transfer functions of this

simple model (STF, STF1 and

STF2) have been optimized by

simulating the DWS model

behavior and comparing the

waveforms to similar SPICE

simulation. STF models the

quadratic dependence of the drain

current versus the gate source

voltage in saturation condition

while STF1 models the transition

between linear and saturation

region.

Fig. 1 shows a typical semicustom

standard cell topology with a

couple of external power and

ground rings for I/O buffers and

input protection and another couple

of internal rings for pre buffer and

logic core. A 9-nor ring oscillator

4

101

301 201

401

2

9

90

81

power pads

power pads power pads

power pads

16mA

16mA

16mA

16mA

IVIVIVIV

7

driv. rec. rec.

9 nor ring osc.

rec. rec.

103

203303

403

Fig. 1: CMOS integrated circuit scheme (transmission line model).

operating at about 40 MHz is used

as core noise generator. Four 16mA

bus drivers (with 50pF external

load) are used as I/O switching

noise generator.

All the internal connections are

modeled by means of transmission

lines, as well as the package pins (a

PGA has been modeled in this

case).

A first level of clock tree

distribution is used to evaluate the

effects of the noise caused by the

simultaneous switching of the

peripheral output drivers on the

internal signals (in the logic core)

in terms of skew on jitter.

POWER AND GROUND

SIMULTANEOUS SWITCHING

NOISE WITHIN THE CHIP

Fig. 3 shows the simulated power

and ground noise for the following

power distribution topology:

a) only a couple of VDD and GND

pads used;

b) two couples of

VDD and GND

pads used at

opposite corner

of the chip;

c) four couples

of VDD and

GND pads used,

one for each

corner of the

chip.

A double

bonding has been

considered for

both VDD and

GND signals. For

double bonding

is intended a

normal procedure

sometimes used

in the definition

of the bonding

diagram

(connection chip-

package) in order

to reduce the

number of package pins dedicated

for power and ground. Using this

procedure, two different power

pads on chip, related to internal and

external power ring pads, are

bonded to the same package cavity

pin. As result, the two power

distributions for logic core and

output buffers are decoupled on

chip but a not-negligible coupling

effect has been noted, due to the

common interconnection through

the package.

The simulations show the voltage

transients on both power and

ground rings probed at two opposite

corners of the chip. Fig. 3a shows

that it is possible to have different

values of the power ( V 0.3V) at

the same time and different

locations due to noise wave

propagation within the rings. This

effect decreases with the increasing

of the pads number for power and

ground on chip and their uniform

distribution around the chip

boundary.

Due to the ring structure of power

and ground distribution, and the

periodic occurrence of the noise

stimulus, some areas on the chip are

noisier than others, due to noise

wave interference. This stationary

behavior depends on noise

frequency, on time constants

presented by the power ring

distribution and power pads

location (that cause

discontinuities). It is interesting to

note that, for this particular case,

the configuration b) shows less

peak-to-peak noise than the

configuration c).

OUTPUT WAVEFORMS

STF TD1 TD2

Vds

STF1

G

D

Ids

Vgs

k

Vds

STF STF1

S

STF 2

Cgs

Cds

Cgs

k1

k*Ids

STF2

Ids

Vgs

k

Vds

STF STF1

k1

k*Ids

STF2

N_channel

P_channel

Vgs

Fig. 2: Example of macro model structure for MOS transistor with

the p-channel and n-channel static transfer function.

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TIME[nS]

-2.00 V

-1.10 V

-0.20 V

0.70 V

1.60 V

2.50 V

3.40 V

4.30 V

5.20 V

6.10 V

7.00 VV(101)

V(201)

V(103)

V(203)

Fig. 3a: Power & ground voltage noise (1 P&G couple)

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TIME[nS]

-3.00 V

-2.00 V

-1.00 V

0.00 V

1.00 V

2.00 V

3.00 V

4.00 V

5.00 V

6.00 V

7.00 VV(81)

chip_1.g

V(81)

chip_2.g

V(81)

chip_4.g

a

bc

Fig. 4: Output driver voltage (a=1 P&G couple, b=2 P&G couples, c=4 P&G couples)

Due to the ground bouncing effects

the output signals present an

overshoot and undershoot of about

2 V (Fig. 4). Increasing the number

of power pads, the slew-rate

increases, so that the signals show

more noise (no slew-rate control

has been assumed for the buffers

used).

BONDING AND INTERNAL

NOISE

Fig. 5 shows the differences

between a chip supplied by double

bonded pads (first four

simulations), or independent VDD

and GND package pins for I/O and

logic core. It is possible to note the

noise shape and level differences on

internal power and ground rings

(nodes 301 and 401) for the two

configurations. In particular, in the

first case, the noise is mainly

correlated to the noise source in the

core.

The signal V(90) is the ring

oscillator output and it is shown as

reference for noise correlation of

ring bounces.

CLOCK SKEW AND NOISE

MARGIN EVALUATION

An internal clock signal (Fig. 6a

and 6b) has been analyzed at the

driver output and at the input of

two far receivers; the signals are

displayed using eye-diagrams. It

is possible to see that the

propagation shows about 1ns of

delay, 500ps of skew between the

receiving taps and 500ps of jitter

due to simultaneous switching

noise. Simulations performed

using the RC (lumped or

distributed) model for the same

clock tree interconnection

showed a delay evaluation which

is 30% lower than the result

obtained using TLM models.

CONCLUSION

The increasing speed of

semicustom IC technologies leads

to a growing impact on system

performance of on-chip signal

integrity issues related to both

signal interconnection and power

bouncing effects. Accurate models

of interconnecting paths are needed

in order to get reliable results from

simulations and choose the best on-

chip interconnect structure. TLM

for both lossy slow-wave

interconnect and for package

effects is needed. This in turn

requires the use of next generation

simulation tools which are able to

deal with a large number of

transmission lines at very small

time-step (in the range of 5ps for

CMOS technology).

In this way the IC designer can

quickly evaluate several design

alternatives for power supply,

signal interconnections and

packaging issues. Transmission line

propagation on both signal and

noise paths frequently leads to

difficult to predict or unexpected

effects that can have a major impact

on choosing the internal chip

architecture.

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TIME[nS]

-2.00 V

-1.10 V

-0.20 V

0.70 V

1.60 V

2.50 V

3.40 V

4.30 V

5.20 V

6.10 V

7.00 V V(101)

V(201)

V(103)

V(203)

Fig. 3c: Power & ground voltage noise (4 P&G couples)

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TIME[nS]

-2.00 V

-1.10 V

-0.20 V

0.70 V

1.60 V

2.50 V

3.40 V

4.30 V

5.20 V

6.10 V

7.00 VV(101)

V(201)

V(103)

V(203)

Fig. 3b: Power & ground voltage noise (2 P&G couples)

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TIME[nS]

-1.14 V

1.16 V

V(101)chip_2.g

3.96 V

6.10 V

V(201)chip_2.g

-1.12 V

1.14 V

V(301)chip_2.g

3.94 V

5.88 V

V(401)chip_2.g

-1.18 V

1.41 V

V(101)chip_2_spt.g

3.71 V

6.10 V

V(201)chip_2_spt.g

-1.17 V

0.91 V

V(301)chip_2_spt.g

4.21 V

5.97 V

V(401)chip_2_spt.g

-0.75 V

5.59 V

V(90)chip_2.g

Fig. 5: Power and ground noise with double or single bonding

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TIME[nS]

-1.00 V

6.00 V

V(2)

-1.00 V

6.00 V

V(7)

-1.00 V

6.00 V

V(9)

Fig. 6a: Internal clock signal: eye diagrams (2 P&G couples, single bonding)

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TIME[nS]

-0.82 V

5.75 V

V(2)

-0.76 V

5.73 V

V(7)

-0.72 V

5.69 V

V(9)

Fig. 6b: Internal clock signal: eye diagrams (2 P&G couples, double bonding)