PB 1990-2009 AN 02

HDT Copyright 1990

D W N & D W V

M O D E L I N G O F A C T I V E C O M P O N E N T S

The fast growth of signal integrity

and EMC problems of digital

systems requires very accurate

modeling techniques of active

components, especially regarding

their dynamic behavior at high

speed. On the other hand, the

growing complexity of systems

imposes severe goals regarding the

simulation speed. As known the

two requirements of speed and

accuracy are opposite, so that the

traditional approach to these

problems leads to unsatisfying

results. SPICE models, for

example, are not suitable for the

simulation of circuits with more

than few hundred elements,

because the simulation time rises

prohibitively with circuit

complexity and convergence

problems could occur.

Furthermore, the results often don't

reflect the real situations. In fact,

the parasitic effects introduced by

the discontinuities of the package

and the pin bouncing (caused by

simultaneous output switching)

can often invalidate the results. On

the other hand, simple circuital

equivalents, as those utilized in the

transmission line simulators, are

not sufficient to describe the

unpredictable dynamic effects of

real devices.

A behavioral or mixed electrical-

behavioral approach is much more

effective to face real-world

situations, where the effects of

active parts, lossless or lossy

interconnections, EMC constraints,

and electrical, logical and timing

issues must be taken

simultaneously into account.

DWN MODELING

APPROACH

The modeling approach shown in

this application note is based on the

primitives offered by the DWN

simulator and allows the designer to

perform very accurate electrical

simulations with a speed at least

two orders of magnitude greater

than other commercial products1.

This modeling procedure is simple

and the data can be collected from

several sources. In particular, it is

possible to extract model

parameters from datasheet, from

analog simulations (SPICE, ELDO,

etc.) or, better, directly from

TDR (Time Domain

Reflectometer) measurements.

Thanks to this fast experimental

approach, the model can take all the

non-linearities of the I/O cells of

the device into account,

1DWN uses a very fast DSP engine that

assures high speed without convergence

problems.

DUT

TDR

Z0

ground plane

vcc

gnd Vbias

R

Ctdrcoax

Fig. 1: Measurement set-up for TDR characterization.

0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

0.80 #

1.00 ##RHO

A

B

C

D

Fig. 2: TDR response for a CMOS input

PB 1990-2009

as well as its dynamic behavior.

The currents flowing through the

model are simulated with accuracy

and can be used for ground

bouncing noise analysis and EMI

verifications. Furthermore, these

TDR-based models are typically

wideband2 and are suitable for

EMC analysis of even slow

components.

SIMPLE CMOS INPUT

This section is dedicated to the

modeling of a CMOS input without

protection diodes. The model is

based on experimental

reflectometer characterizations of

the input stage of the device. The

test-fixture is shown in Fig.1. The

TDR output pulse (typically a

voltage step with 250mV amplitude

and 25ps rising edge) is fed to the

input pin of DUT package via a

DC-block capacitor and a semi rigid

50 coax cable. The realization of

the test-fixture must take all high-

speed issues into account, so that

ground and Vdd supply planes must

be provided and the interconnection

of the device to the fixture must

reflect that of real operation. The

connection of the launch cable to

2 Current TDR analysis offers band up to

40 GHz.

the package must be kept as short

as possible.

The DC biasing of the input is

obtained via a variable supply

(Vbias). The resistor R is chosen as

high as possible, in order to provide

a high-impedance path for the

reflectometer, but low enough to

bias the input at the desired level.

A typical TDR response is shown

in Fig.2 where it is possible to

identify four sections: the peak

identified by the label A is the

parasitic effect due to the launch

cable where it is connected to the

device under test.

The section B is related to package

and package-die bond effects. The

section C shows the dynamic

behavior of the input circuitry (the

reactive effects of the input gates in

this particular case). The final value

of the transient C (point D) is the

reflection coefficient determined by

the input ohmic resistance of the

device under test in parallel with

the biasing resistor R. It is possible

to compensate the error introduced

by the resistor R with the insertion

of a negative resistor -R in the

model description, as shown in

Fig.3. Sweeping the bias voltage

within the possible operation range

(0V - 5V) there is no practical

deviation of the behavior shown in

Fig.2, so that a simple linear model

is suitable for this situation. The

choice is a mixed TLM

(Transmission Line Modeling) and

BTM (Behavioral Time Modeling)

approach. In particular the package

effect can be modeled as a short

transmission line, while the

behavior of the active input is

directly modeled by a PWL one-

port scattering element (Bin)3. The

separation of package effects

allows the user to simulate the

behavior of internal input node so

that it is possible to extrapolate

device responses with other

packages. If this is not required, a

whole BTM model can include the

package effects.

3 The PWL (PieceWise Linear) fitting of

Bin is easily extracted from the actual

behavior using the MCS (Model Capture

System) facility of DWV.

.SUBCKT INCMOS 1 2

* TLM model of package

TIN 1 0 3 0 Z0=75 TD=200PS

* input dynamic behavior

BIN 3 0 S11=PWL(0 0.2 30PS -0.6 0.6NS -0.5 1.5NS 0.7 2.5NS

+ 0.85 5NS 1.0) Z0=50 TD=0

* voltage shifter ("0" -> 0V, "1"->1V)

E1 2 0 4 0 PWL(0V 0 2.4V 0 2.6V 1 5V 1)

.ENDS INCMOS Fig. 4: Simple CMOS input model description (DWN syntax).

1 Tin

Z0,Td

Bin -R

STF Vout

Vin

2

E1

+ 0

0

1

5

Fig. 3: Simple CMOS input model including logic level shift.

ASvdd

ASgnd

Pvdd

Pgnd

Bdvdd

Bdgnd

VDD 10

GND 20

1 T in

Z0,Td

Bin

STF Vout

Vin

2

0

0

1

5

E1

+

Fig. 5: CMOS input model including protection diodes and supply pins.

PB 1990-2009

In order to simulate the I/O timing

properties of the device it is

possible to include in the model the

input static transfer characteristics

of the device with output values

shifted to the logical state "0" and

"1". In this way the model is

directly interfaceable to a core

block able to model the timing logic

behavior of the component. Fig.4

shows DWN net list of the model

composed by the Bin block and the

transmission line that models the

package contribution. The level

shifter completes the model. DWN

uses a SPICE-like syntax and this

model can become a DWN sub

circuit.

Upon the model is completed, it is

possible to validate it through a

simulation of the measure set-up

that has been used during the

characterization (see App.A).

CMOS INPUT WITH

PROTECTION DIODES.

Usually, a CMOS input has two

clamping diodes for protection

against electrical discharge, so an

accurate model must take both their

non-linear and dynamic effects into

account, as shown in Fig.5. In this

situation it is necessary to introduce

the effect of power and ground pins

because during the clamping action

the diode current flows through

them.

Often each diode has a specific

static and dynamic behavior.

Sometimes the static characteristic

is available from the datasheet with

a format similar to tab.1. Biasing

the device at 5.7V (on the DUT

pin) it is possible to test the

clamping effect toward the supply,

while a bias voltage of -0.7V

tests of the ground clamping diode.

By changing the current in

clamping conditions, it is possible

to collect a family of reflectometer

responses for each protection diode.

Fig.6 shows an example of these

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

Iclamp=0.2MA

Iclamp=1MA

Iclamp=5MA

Iclamp=20MA

a)

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

Fig. 7: PWL fitting of a clamping diode reflectometer response: the last sample is

extrapolated to -1000m .

V (V) I(mA)

0.00 0.0

0.50 0.1

0.55 0.3

0.60 0.9

0.65 1.8

0.68 3.8

0.70 10.7

0.72 25.4

Tab.1: Example of static charac-

teristic of clamping diode.

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

Iclamp=20MA

Iclamp=5MA

Iclamp=1MA

Iclamp=0.5MA

b) Fig. 6: Reflectometer response of protection diodes versus clamping current: a) VDD diode,

b) GND diode.

PB 1990-2009

graphs for a CMOS EPROM in DIL

package. It is interesting to observe

the different behavior of the two

diodes.

The ground diode shows a very fast

response so that low impedance

levels are reached in about a

nanosecond. On the contrary, the

Vdd diode shows a slow transient

(several nanoseconds long) before

it reaches low impedance levels.

This slow behavior obviously has

significant impact in the clamp

action, so that, if a voltage

overshoot due to reflections occurs,

it will be effectively clamped only

after the delay observed in the TDR

characterization. This kind of

situation is very common and

difficult to forecast. This modeling

approach, based on TDR

measurement, is the best way to

pinpoint these effects. Furthermore,

during the modeling, the user gets

also a lot of information, not

supplied by the manufacturer,

concerning the "quality" of the

component he is going to use.

To complete the model shown in

Fig.5 the following procedure is

suggested:

- extract the package and Bin

descriptions as already explained

for the model of Fig.3;

- determine the static input

characteristic of the DUT in normal

and clamping conditions. The data

can be extracted from datasheet (if

available) or directly from V-I

measurements and used for Pvdd

and Pgnd (non-linear resistors)

descriptions;

- plot the TDR dynamic behavior

of both protection diodes in

clamping condition (with a suitable

value of clamping current4). The

bottom value of the response,

always higher than -1000m (for

typical CMOS protection diodes

the value ranges from -700m to

-900m ), is the reflection

coefficient related to the ohmic

resistance of the diode. Because

this resistance has been already

taken into account by the non-

linear resistor Pvdd and Pgnd, it is

necessary to compensate this effect

during the PWL extraction with the

related utility MCS of DWV, as

shown in Fig.7.

The dynamic behavior of the VDD

and GND path through the supply

pins is easily modeled in a

behavioral way. This can be

accomplished by means of the two

S-parameter blocks Bdvdd and

Bdgnd obtained as PWL fittings of

actual TDR behaviors. The two

series adaptors ASvdd and ASgnd

are used to connect the blocks in

series to the supply paths. In fact

the series adaptor connects the one-

4 It is suggested to increase the clamping

current up to its maximum limits.

DTF

t

DTF

STF

Vout

Vin

1

Vout

Vout

Z0,Td

E2

20 GND internal

2

Boutsw2

sw1

Pvdd

Pgnd

t

E1

10 VDD internal

Fig. 8: CMOS output behavioral (BTM) model.

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

1MA

2MA

5MA

10MA

20MA

Fig. 10: TDR responses for an ECL output versus biasing current.

Vcontrol

R( )

1

1K

1M

5 2.5

sw2 sw1

Fig. 9: Static characteristics of the two

switches.

PB 1990-2009

port element placed at its third port

between the two nodes

corresponding to its remaining

ports.

The TDR dynamic behavior of the

diodes in clamping conditions

takes into account the

contributions of all the elements

present along the signal path and,

in particular, the package effect of

the input pin, the diode

capacitance, the on-chip power and

ground rails and the bonding and

package effects of the power pins.

If the diode is a "good diode" (that

means that the low impedance

condition is achieved in less than 1

ns), its intrinsic dynamic effect is

negligible compared with the

power and ground distribution

effects, so that the blocks Bdvdd

and Bdgnd can be obtained from

the measured dynamic behavior of

the power pins5. This model

allows accurate simulation of the

5 Extracted from TDR characterizations of

the power pins.

pin bouncing phenomena, as it will

be discussed later.

CMOS OUTPUT.

Typically, the outputs of a CMOS

driver act as linear resistor until a

determined output current level is

reached. Increasing the current

level, the output enters the

saturation region, where its

resistance grows.

Other non-linear effects are

introduced by the output clamp

diodes. The proposed model

accepts logic levels (0,1) as input

and the first STF block (Static

Transfer Function) shifts the

incoming (logic levels) signal to the

desired output levels. The two

dynamic transfer functions (DTF)

model the actual behavior of the

output waveform without load.

The dynamic behavior of the

clamping diodes is taken into

account by the dynamic model of

the power pins, as discussed in the

previous section. The switching

between the two logical states is

performed by two switches

controlled by the output voltage

itself. The two switches,

implemented by voltage controlled

resistors, have low impedance when

closed in order to not affect the

output impedance value. Fig. 9

shows suggested static transfer

characteristics that could be used to

control the switch resistance. The

current flowing from VDD to the

load during the 0->1 transition and

from the load to GND during the 1-

>0 transition is accurately modeled.

Because the switches transitions are

not abrupt, also the current feed

through between power and ground

during the transitions is modeled, a

typical effect of CMOS circuitry.

The two dynamic characteristics are

modeled directly from

measurements of the output voltage

transient with the driver unloaded,

using PWL fitting. The non-linear

resistors represent the static

characteristics of the output stage in

both normal and clamping

conditions.

The Bout block models the dynamic

behavior of the output in normal

operating condition.

A description of the package

completes the model.

ECL OUTPUT

An ECL device presents a strong

non-linearity of the output

resistance at low current levels. In

fact, the ECL output is

implemented by a bipolar emitter

follower that has low output

resistance (normally less than 10

at 10mA biasing) for normal

operating current. During the 1-> 0

transition there are situations in

which the output transistor goes

near cut-off and its output

impedance greatly increases. Fig.10

shows the reflectometer response of

an ECL output with different

biasing current for both "1" and "0"

logic states. It is possible to point

out the sensitivity of the ohmic

resistance (given by the right-end

steady-state responses) versus the

current.

out1

out2

outn

in1

in2

VDD

GND

Bvdd

Bgnd

AS

AS

OUT

OUT

OUT

OUT

IN

IN

IN

INinm

Timing/logic

CORE

(logic levels)

Fig. 12: Complete device model including logic/timing behavior and simultaneous

switching noise effect.

STF Vout

Vin

1

2 ToutASPout

Eout

20 GND

+

DTF Vout

t

Z0,Td

Bout

Fig. 11: ECL output behavioral model

PB 1990-2009 The dynamic behavior is usually

the same for both "0" and "1" logic

states6 as well as the static output

characteristics. The model structure

is shown in Fig.11.

The static transfer function

translates the signal from the logic

input levels to ECL output levels.

The dynamic transfer function has

been represented by a PWL fitting

of the output waveform (driver

unloaded). The non-linear resistor

is described using the V-I static

characteristic of the output. The

Bout and package models are

extracted with the same procedure

described in the previous sections.

The pin #20 can be connected

directly to GND or to other

circuitry taking pin bouncing

effects into account.

PIN BOUNCING EFFECT

All the models proposed for input

and output sections of the device

are suitable for simulations that

take the simultaneously switching

noise into account. The model of a

complex I/O section of a device

with package effects is shown in

Fig.12.

All the I/O models are coupled by

the dynamic behavior of the power

and ground rails on chip, by the

bonding wires and the package

itself. The Bdvdd and Bdgnd

elements are used once and replace

all the dynamic models of the

clamping diodes for both input and

output models (with the exception

of "slow" diodes, as previously

mentioned). The power and ground

coupling allows a good simulation

of the pin bouncing effect in both

normal and clamping operating

conditions. It is interesting to point

out that the macro model (that is

described as a sub circuit using the

SPICE-like syntax of DWN)

couples the input section of the

device with the output one. As a

consequence, the noise due to the

6 In fact, a unique transistor is active for

both the logical states.

output drivers affects the input

stage operation.

The core sections model the

internal logical functions of the

device which can be represented by

logical functions (AND, OR, etc).

The logic behavior can be modeled

in DWN using voltage controlled

switches.

With a correct introduction of

delays along the input, core, or

output sections, the macro model

allows accurate electrical, timing

and logic simulation at the same

time.

CONCLUSION

The effects of high-speed operation

of active devices are very complex

and involve several phenomena.

The only way to get accurate

models is through experimental

characterization that can take all the

effects into account, pinpointing

unusual operation modes that often

occur. DWN & DWV allow direct

utilization of the experimental

measures to build very accurate and

reliable models without resorting to

circuital equivalent.

In this way the user is able to build

up his own library of DWN models

of active and passive components.

These models can be utilized for

fast and accurate simulation of

digital systems both in the pre-

layout and in the post-layout phase

of the design. In order to automate

this type of analysis, DWN &

DWV are interfaced to the most

popular CAD/CAE environments

through a specific tool (PRESTO)

allowing accurate and exhaustive

simulation of PCB boards in short

times (~1 hour). The wide-

bandwidth models are also suitable

for EMC analysis and in very high-

speed applications involving the

use of new packaging and

interconnection technologies, like

the MCMs (Multi-Chip Modules).

APPENDIX A

This section describes the

validation of the device model that

has been created using the

behavioral approach. The model is

validated through a simulation of

the same measure set-up that has

been used for device

characterization. The model is

validated by direct comparison of

the simulated waveforms with the

actual ones. A very fast step (25ps)

simulates the TDR pulse. Due to the

decoupling capacitor connected to

the TDR, the initial transient during

the simulation could be very long.

In fact, the TDR step must be only

activated after the initial transient is

exhausted and when the device is

biased at the proper operating point.

Fig.13 shows a scheme that can be

used for the simulation of TDR

responses. At time 0 the switch sw1

is open and the switch sw2 is

closed. The bias generator can be a

current generator with very high

internal impedance or a voltage

generator with an internal resistor

greater than 10k . The circuit is

designed in order to use a current

generator for current greater than

100µA (for example validating

clamping diodes) and a voltage

generator for current lower than

100µA (for example testing

+ 25mV/25ps

t 55ns

Vtdr

1 +

E1=Vcs Ctdr sw1

sw2

Cs=1pF

td=50ns

Bias

Model

under

test

Fig. 13: Simulation scheme for model validation.

PB 1990-2009 elements with very high input

impedance). The values of the

current or voltage bias can be

positive or negative (source or

sink). After 50ns the device is

biased at the correct operating point

and the generator E1 copies the

voltage present at the pin of the

model. At this time, the two

switches change condition and a

step of 25mV amplitude and 25ps

rise time is fed to the model. The

amplitude of the signal at the test

point 1 multiplied by 80 (because

of the 25mV step) gives the

reflectometer response scaled

between -1000m and +1000m in

order to provide a direct

comparison to the TDR measure.