The top documents tagged [chip network]

Sony Chassis Eg1h
Documents Sony Chassis Eg1h

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Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems Érika Cota Luigi Carro Flávio WagnerMarcelo Lubaszewski UFRGS Porto Alegre, Brazil
Documents Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems Érika Cota Luigi Carro Flávio WagnerMarcelo Lubaszewski UFRGS Porto Alegre, Brazil

220 views

Department f Computer Engineering Malaviya National Institute of Technology, Jaipur India (PROM3D) Parameterized Path-Based, Randomized, Oblivious, Minimal
Documents Department f Computer Engineering Malaviya National Institute of Technology, Jaipur India (PROM3D) Parameterized Path-Based, Randomized, Oblivious, Minimal

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Intel Redefines GPU: Larrabee Tianhao Tong Liang Wang Runjie Zhang Yuchen Zhou
Documents Intel Redefines GPU: Larrabee Tianhao Tong Liang Wang Runjie Zhang Yuchen Zhou

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Conference on Adaptive Hardware and Systems (AHS'14) - FlexTiles FPGA Emulation
Engineering Conference on Adaptive Hardware and Systems (AHS'14) - FlexTiles FPGA Emulation

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Embedded system
Engineering Embedded system

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STRUCTURED CODESIGN FOR MANYCORE SYSTEMS Jürg Gutknecht & Lisa (Ling) Liu, ETH Zürich Sofsem Novy Smokovec, January 2011
Documents STRUCTURED CODESIGN FOR MANYCORE SYSTEMS Jürg Gutknecht & Lisa (Ling) Liu, ETH Zürich Sofsem Novy Smokovec, January 2011

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The Migration of Safety-Critical RT Software to Multicore Marco Caccamo University of Illinois at Urbana-Champaign
Documents The Migration of Safety-Critical RT Software to Multicore Marco Caccamo University of Illinois at Urbana-Champaign

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An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs Gaoming Du 1, Miao Li 1, Zhonghai Lu 2, Minglun Gao 1, Chunhua
Documents An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs Gaoming Du 1, Miao Li 1, Zhonghai Lu 2, Minglun Gao 1, Chunhua

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Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs Hiroki Matsutani Michihiro Koibuchi Daisuke Ikebuchi Kimiyoshi Usami Hiroshi Nakamura
Documents Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs Hiroki Matsutani Michihiro Koibuchi Daisuke Ikebuchi Kimiyoshi Usami Hiroshi Nakamura

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Hyunbean Yi, Sungju Park, and Sandip Kundu, Fellow, IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I : REGULAR PAPERS, VOL. 57, NO. 7, JULY 2010 Reporter:
Documents Hyunbean Yi, Sungju Park, and Sandip Kundu, Fellow, IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I : REGULAR PAPERS, VOL. 57, NO. 7, JULY 2010 Reporter:

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Network-on-Chip An Overview System-on-Chip Group, CSE-IMM, DTU
Documents Network-on-Chip An Overview System-on-Chip Group, CSE-IMM, DTU

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