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TRADITIONAL CMOS DESIGN
25/12/2016 Imran Ullah Khan JAP/IU 1
Outline
CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Stick Diagrams
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CMOS Gate Design
A 4-input CMOS NOR gate
A
B
C
DY
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Complementary CMOS Complementary CMOS logic gates
• nMOS pull-down network• pMOS pull-up network
X (crowbar)0Pull-down ON
1Z (float)Pull-down OFFPull-up ONPull-up OFF
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pMOS pull-up network
nMOS pull-down network
Series and Parallel
nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
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Conduction ComplementComplementary CMOS gates always produce 0 or 1
Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS
Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel
A
B
Y
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Compound Gates Compound gates can do any inverting function Ex: AND-AND-OR-INV (AOI22)
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
)()( DCBAY
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Example:
A B
Y
C
D
DC
B
A
DCBAY )(
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Pass Transistors Transistors can be used as switches
g
s d
g
s d
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Pass Transistors
Transistors can be used as switchesg
s d
g = 0s d
g = 1s d
0 strong 0Input Output
1 degraded 1
g
s d
g = 0s d
g = 1s d
0 degraded 0Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
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Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
g = 0, gb = 1a b
g = 1, gb = 0a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1, gb = 0
g = 1, gb = 0
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Tristates
Tristate buffer produces Z when not enabled
111001Z10Z00YAEN
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Multiplexers 2:1 multiplexer chooses between two inputs
1X11
0X01
11X0
00X0
YD0D1S
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Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
S
S
D0
D1YS
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D Latch When CLK = 1, latch is transparent
Q follows D (a buffer with a Delay) When CLK = 0, the latch is opaque
Q holds its last value independent of D a.k.a. transparent latch or level-sensitive latch
D
CLK
Q
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Gate Layout Layout can be very time consuming
Design gates to fit together nicely Build a library of standard cells Must follow a technology rule
Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts
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Example: Inverter
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Inverter, contd..
Layout using Electric
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Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40
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NAND (using Electric), contd.
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Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers
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Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers
VinVout
VDD
GND
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Wiring Tracks A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track
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Area Estimation Estimate area by counting wiring tracks
Multiply by 8 to express in
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Example: Sketch a stick diagram for O3AI and estimate area
DCBAY )(
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Example:
Sketch a stick diagram for O3AI and estimate area DCBAY )(
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