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VLSI Project4 bit Comparator
Submitted To
Fariah HayeeLecturer,
Faculty of EEE,BUET
Maruf AhmedLecturer,
Faculty of EEE,BUET
Submitted By
Ashik Amin Mohammad Wahiduzzaman Khan
Std ID #0806098 Std ID #0806144
Group 27
Outline
• Specification, Architectural Design and Functional Verification
• Gate Level Schematic Design• Transistor Level Design and Cell Layout• Layout Placement and Routing• Layout of Full Chip, DRC & LVS Log
Characteristic of a Comparator
Input Output
Ai Bi Di+1 Ci+1 Ci Di
x x 1 0 1 0
x x 0 1 0 1
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 0 0
X signifies “don’t care”
Schematic
This type of cascade-able connection lessens the number of not gates reqd (2 for each block). Thus reducing the area of layout
significantly.COMPCELLA COMPCELLBInverted I/P True I/P
True O/P Inverted O/P
Waveform
A B Cout
Dout
4 4 0 02 4 0 12 1 1 07 1 1 0
RTL
Gates’ Schematic and Layout
CompcellA
CompcellB
Comparator
IO Pad
Simulation (ADE L)
Delay 50.8497-50.75=0.0997ns
Average Power 1.324E-6
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