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embedded_system
Embedded System
PART 8 (SPI)ENGKEROLES SHENOUDA
1
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(SPI)
Serial Peripheral Interface
its time to wake up
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SPI (Serial Peripheral Interface)
synchronous data transfer
Full-duplex Single Master multi slave Serial interface
Multiple slave devices are supported through selection with individual slaveselect (SS) lines
The SPI bus was originally started by Motorola Corp (now Freescale) but in recent years has become a widely used standard adapted by many semiconductor chip companies
It can be used to communicate with a serial peripheral device likeexternal EEPROM or with another microcontroller with an SPIinterface
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Advantages of SPI
Higher throughput (Faster)SPI 10Mbs ndash 20Mbs
Simple Receiver Hardware gtgtgt Simple Shift Register
Support Multiple Slaves
Lower power Requirements than I2C
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Disadvantages of SPI
Requires more Pins
Master must control all communications (Slave doesnrsquot issue the transaction)
Separate SS Lines
No Flow Control (must know slave speed)
5
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SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
6
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
(SPI)
Serial Peripheral Interface
its time to wake up
2
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SPI (Serial Peripheral Interface)
synchronous data transfer
Full-duplex Single Master multi slave Serial interface
Multiple slave devices are supported through selection with individual slaveselect (SS) lines
The SPI bus was originally started by Motorola Corp (now Freescale) but in recent years has become a widely used standard adapted by many semiconductor chip companies
It can be used to communicate with a serial peripheral device likeexternal EEPROM or with another microcontroller with an SPIinterface
3
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Advantages of SPI
Higher throughput (Faster)SPI 10Mbs ndash 20Mbs
Simple Receiver Hardware gtgtgt Simple Shift Register
Support Multiple Slaves
Lower power Requirements than I2C
4
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Disadvantages of SPI
Requires more Pins
Master must control all communications (Slave doesnrsquot issue the transaction)
Separate SS Lines
No Flow Control (must know slave speed)
5
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SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
6
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
11
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
30
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
SPI (Serial Peripheral Interface)
synchronous data transfer
Full-duplex Single Master multi slave Serial interface
Multiple slave devices are supported through selection with individual slaveselect (SS) lines
The SPI bus was originally started by Motorola Corp (now Freescale) but in recent years has become a widely used standard adapted by many semiconductor chip companies
It can be used to communicate with a serial peripheral device likeexternal EEPROM or with another microcontroller with an SPIinterface
3
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Advantages of SPI
Higher throughput (Faster)SPI 10Mbs ndash 20Mbs
Simple Receiver Hardware gtgtgt Simple Shift Register
Support Multiple Slaves
Lower power Requirements than I2C
4
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Disadvantages of SPI
Requires more Pins
Master must control all communications (Slave doesnrsquot issue the transaction)
Separate SS Lines
No Flow Control (must know slave speed)
5
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SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
6
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
7
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
8
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
10
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
11
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
13
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
30
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
38
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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embedded_system
SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system98
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embedded_system
Advantages of SPI
Higher throughput (Faster)SPI 10Mbs ndash 20Mbs
Simple Receiver Hardware gtgtgt Simple Shift Register
Support Multiple Slaves
Lower power Requirements than I2C
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Disadvantages of SPI
Requires more Pins
Master must control all communications (Slave doesnrsquot issue the transaction)
Separate SS Lines
No Flow Control (must know slave speed)
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SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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embedded_system
Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Disadvantages of SPI
Requires more Pins
Master must control all communications (Slave doesnrsquot issue the transaction)
Separate SS Lines
No Flow Control (must know slave speed)
5
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embedded_system
SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI BUS Protocol
These 4 pins SDI
SDO SCLK and CE
make the SPI a 4-
wire interface
The SDI SDO
SCLK and CE
signals are
alternatively
named as MOSI
MISO SCK and SS
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SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
SPI Interface
The SPI bus specifies four logic
signals
bull SCLK(SCKCLK) Serial Clock (output from
master)
bull MOSI(SIMOSDIDI) Master Output Slave Input
(output from master)
bull MISO(SIMOSDODO) Master Input Slave
Output (output from slave)
bull SS (CSCECEN) Slave Select (active low
output from master)
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Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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embedded_system
Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
Master Slave Setup
In this setup there are 3 slave devices The SDO lines are tied together to the SDI line of the master
The master determines which chip it is talking to by the CS lines
For the slaves that are not being talked to the data
output goes to a Hi Z state
Multiple Independent Slave Configuration
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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How SPI works
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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How SPI works
SPI consists of two shift
registers one in the master
and the other in the slave
side
Also there is a clock
generator in the master side
that generates the clock for
the shift registers
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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HOW SPI WORKS
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In)
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out)
The master clock generator provides clock to the shift registers in both the master and
slave
The clock input of the shift registers can be falling- or rising-edge triggered
Shift registers are 8 bits long So after 8 clock pulses the contents of the two shift
registers are interchanged
When the master wants to send a byte of data it places the byte in its shift register and
generates 8 clock pulses
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
30
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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HOW SPI WORKS
After 8 clock pulses the byte is transmitted to the other
shift register
When the master wants to receive a byte of data the slave
side should place the byte in its shift register and after
8 clock pulses the data will be received by the master shift
register
It must be noted that SPI is full duplex meaning that it
sends and receives data at the same time
12
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system98
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
30
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemSPI rdquo Serial Peripheral Interface rdquo
How SPI works
Master Slave
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
30
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemData Transfer in SPI
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
MASTER SLAVE
MOSI MISO
15
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemData Transfer in SPI
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
MASTER SLAVE
MOSI MISO
16
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
20
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SPI With Flash Memories
(custom protocol)
21
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
27
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemData Transfer in SPI
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
MASTER SLAVE
MOSI MISO
17
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemData Transfer in SPI
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6
M7
MASTER SLAVE
MOSI MISO
18
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
28
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
29
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Draw this Setup
ldquoSPI Master Slave Setup
with Multiple slave cascadedrdquo
good question19
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemMaster Slave Setup
Multiple slave cascaded
In this example each slave is cascaded so that the output of one slave is the input of another
When cascading they are treated as
one slave and connecting to
the same chip select
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI With Flash Memories
(custom protocol)
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Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data
To write to the status register the SPI host first enables the slave select line for the current device The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents Since the transaction does not need to return any data the slave device keeps the MISO line in a high impedance state and the master masks any incoming data Finally slave select is de-asserted to complete the transaction
22
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
23
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Simple SPI Read Transaction A status register read transaction would be similar to the write transaction but now takes advantage of
data returned from the slave After sending the read status register instruction the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles The host receives the bitstream and completes the transaction by de-asserting SS
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system98
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Which type of
SPI act as ldquohalf duplexrdquo
serial communication
good question24
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SPI Bus 3-Wire
25
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI Bus 3-Wire
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
26
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus In a 3-wire interface bus we have
SCLK and CE and only a single pin for data
transfer
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol
For that reason a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemSPI Bus 3-Wire and Multi-IO
Configurations
In 3-wire mode MOSI and MISO lines are combined to a single bidirectional data
Transactions are half-duplex to allow for bidirectional communication Reducing the number of data lines and operating
in half-duplex mode also
decreases maximum possible throughput
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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QUAD SPI [QSPI]
Multi IO variants such as dual IO and quad IO add additional data lines to the standard for increased throughput This performance increase enables random access and direct program execution from flash memory (execute-in-place)
A multi IO SPI device is capable of supporting increased bandwidth or throughput from a single device A dual IO (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices
A quad IO (four-bit data bus) interface improves throughput four times
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Example QSPI
connected to
Spansion Flash
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
Quad IO is gaining popularity with flash memories for its increased performance Instead of using a single output and single input interface Quad IO utilizes 4 separate half-duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI
31
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
32
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Conclusion
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Example Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a Spansion S25FL016K serial NOR flash device To read from the device a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated Next the host sends the address since the interface now has 4 bidirectional data lines it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Conclusion
33
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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embedded_system
Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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embedded_system
Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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embedded_system
SPI ON atmega32
38
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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8-bit standard SPI access
bullSPI (Serial Peripheral Interface)
4 wires protocols using MOSI MISO SCLK
and SS
34
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI-3
variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line with bus turn-around phases
35
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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Dual-SPI
variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data
36
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
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SPI ON atmega32
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Quad-SPI
variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data
37
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SPI ON atmega32
38
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_system98
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SPI ON atmega32
38
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI Block Diagram39
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI Master-slave Interconnection40
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI Pin Overrides41
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SS Pin Functionality42
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SS Pin Functionality 43
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with SPI
SPCR ndash SPI Control Register ndash This register is basically the master register ie it contains the bits to initialize SPI and control it
SPSR ndash SPI Status Register ndash This is the status register This register is used to read the status of the bus lines
SPDR ndash SPI Data Register ndash The SPI Data Register is the readwrite register where the actual data transfer takes place
44
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemSPCR ndash SPI Control Register
Bit 7 ndash SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set
Bit 6 ndash SPE SPI Enable
When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations
Bit 5 ndash DORD Data Order
When the DORD bit is written to one the LSB of the data word is transmitted first
When the DORD bit is written to zero the MSB of the data word is transmitted first
Bit 4 ndash MSTR MasterSlave Select
This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS
is configured as an input and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR
will become set The user will then have to set MSTR to re-enable SPI Master mode
45
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SPCR ndash SPI Control Register
Bit 3 ndash CPOL Clock Polarity
Bit 2 ndash CPHA Clock Phase
46
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SPCR ndash SPI Control Register
Bits 10 ndash SPRn SPI Clock Rate Select [n = 10]
47
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SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_system
SPSR ndash SPI Status Register
Bit 7 ndash SPIF SPI Interrupt Flag
1 When a serial transfer is complete the SPIF Flag is set An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled
2 If SS is an input and is driven low when the SPI is in Master mode this
will also set the SPIF Flag SPIF is cleared by hardware when executing the
corresponding interrupt handling vector
Alternatively the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set then accessing the SPI Data Register (SPDR)
48
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SPSR ndash SPI Status Register
Bit 6 ndash WCOL Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data
transfer
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set and then accessing the
SPI Data Register
49
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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SPSR ndash SPI Status Register
Bit 0 ndash SPI2X Double SPI Speed Bit
50
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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embedded_system
Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
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Lab 1
First Clock Edge LSB goes at end
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Lab1 transmit a character
between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
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embedded_systemSPDR ndash SPI Data Register is a
readwrite register
The SPI Data Register is a readwrite register used for data transfer between the Register File and theSPI Shift Register Writing to the register initiates data transmission Reading the register causes the ShiftRegister Receive buffer to be readbull SPID7 is MSBbull SPID0 is LSB
51
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Code Sequence
Before you start data transmission you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR
You can operate in either master or slave modes
Master operating mode
If you want to work in master mode you should set the MSTR bit to one Also you should set SCK frequency by setting the values of SPI2X SPR1 and SPR2
Then you should enable SPI by setting the SPIE bit to one before you start data transmission
Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator
After shifting the last (8th) bit the SPI clock generator stops and the SPIF flag changes to one
52
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_system
Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock
Notice that you cannot write to the SPI Data Register
before transmission is completed otherwise the
collision happens
To get the received data you should read it from SPDR
before the next byte arrives
We can use interrupts or poll the SPIF to know when a
byte is exchanged
53
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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embedded_system
Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_system98
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embedded_system
Code Sequence on Master Mode define F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_MasterInit(void)
Set MOSI SCK and SS as Output Pins
DDRB |= (1ltltMOSI) | (1ltltSCK) | (1ltltSS)
DDRB amp= ~(1ltltMISO) Set MISO as an Input Pin
Enable SPI Master mode Shift Clock = CLK 16
SPCR = (1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)
54
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Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
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embedded_system
Code Sequence on Master Mode
unsigned char SPI_MasterTransmit(unsigned char cData)
SPDR = cData Start transmission
while((SPSR amp (1ltltSPIF))) Wait for transmission complete
return SPDR return the received data
55
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_systemInitialize SPI Master Device (with
SPI interrupt) Initialize SPI Master Device (with SPI interrupt)
void spi_init_master (void)
Set MOSI SCK as Output
DDRB=(1ltlt5)|(1ltlt3)
Enable SPI Set as Master
Prescaler Fosc16 Enable Interrupts
The MOSI SCK pins are as per ATMega8
SPCR=(1ltltSPE)|(1ltltMSTR)|(1ltltSPR0)|(1ltltSPIE)
Enable Global Interrupts
sei()
56
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hereLEARN_IN DEPTH
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embedded_system
Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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hereLEARN_IN DEPTH
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embedded_system
Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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embedded_system
Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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MAX7221 data packet format 79
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MAX7221 data packet format
80
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Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_system
Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave the function of the SPI interface depends on the SS pin If the SS is driven high MISO is tri-stated and the SPI interface sleeps Only the contents of SPDR may be updated in this state
When SS is driven low the data will be shifted by incoming clock pulses on the SCK pin
SPIF changes to one when the last bit of a byte has been shifted completely Notice that the slave can place new data to be sent into SPDR before reading the incoming data this is because in AVR there are two one-byte buffers to store received data
57
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Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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Lab 1
First Clock Edge LSB goes at end
61
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Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Lab1 transmit a character between two ATmega32
microcontrollers
64
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Lab1 transmit a character between two ATmega32
microcontrollers
65
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Lab1 transmit a character between two ATmega32
microcontrollers
66
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Lab1 transmit a character between two ATmega32
microcontrollers
67
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Lab1 transmit a character between two ATmega32
microcontrollers
68
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Lab1 transmit a character between two ATmega32
microcontrollers
69
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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embedded_system
MAX7221 data packet format
80
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embedded_system81
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Code Sequence on Slave Mode
In slave mode there is no need to set SCK frequency because the SCK is generated by the master
But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device)
Finally you should enable the SPI by setting the SPIE bit of SPCR to one
58
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hereLEARN_IN DEPTH
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embedded_system
Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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embedded_system
Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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embedded_system
Lab 1
First Clock Edge LSB goes at end
61
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embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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MAX7221 data packet format
80
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embedded_system81
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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embedded_system98
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embedded_system
Code Sequence on Slave Modedefine F_CPU 1000000UL define crystal frequency for delayh
include ltavriohgt standard AVR header
include ltutildelayhgt
define SS 4 Slave Select is Bit No4
define MOSI 5 Master Out Slave In is Bit No5
define MISO 6 Master In Slave Out is Bit No6
define SCK 7 Shift Clock is Bit No7
void SPI_SlaveInit(void)
DDRB |= (1ltltMISO) Set MISO as an Output Pin
Set MOSI SCK and SS as Input Pins
DDRB amp= ~(1ltltMOSI) amp ~(1ltltSCK) amp ~(1ltltSS)
Enable SPI as a Slave Device
SPCR = (1ltltSPE)
59
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Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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embedded_system
Lab 1
First Clock Edge LSB goes at end
61
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embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format 79
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
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hereLEARN_IN DEPTH
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embedded_system
Code Sequence on Slave Mode
unsigned char SPI_SlaveReceive(unsigned char cData)
SPDR = cData send cData to master
Wait for reception complete
while((SPSR amp (1ltltSPIF)))
Return received data
return SPDR
60
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embedded_system
Lab 1
First Clock Edge LSB goes at end
61
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Follow us
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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embedded_system
MAX7221 data packet format
80
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embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
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embedded_system98
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embedded_system
Lab 1
First Clock Edge LSB goes at end
61
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embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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embedded_system
MAX7221 data packet format
80
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embedded_system81
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character
between two ATmega32
microcontrollers
62
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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embedded_system
SPIh88
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hereLEARN_IN DEPTH
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embedded_system
SPIh89
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hereLEARN_IN DEPTH
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SPIc90
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hereLEARN_IN DEPTH
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embedded_system
SPIc
91
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
master slave
Master send Ascending Counter value
Slave send descending Counter value
63
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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embedded_system
MAX7221 data packet format 79
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embedded_system
MAX7221 data packet format
80
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embedded_system81
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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SPIc92
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Think in depth
In your opinion What is the main
issue on this Driver
93
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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hereLEARN_IN DEPTH
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embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
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embedded_system98
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
64
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
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embedded_system
SPIh88
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hereLEARN_IN DEPTH
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embedded_system
SPIh89
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embedded_system
SPIc90
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embedded_system
SPIc
91
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
65
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
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embedded_system
SPIh88
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embedded_system
SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
66
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
67
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
68
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
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SPIh88
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SPIh89
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SPIc90
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SPIc
91
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a character between two ATmega32
microcontrollers
69
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
70
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
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embedded_system98
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hereLEARN_IN DEPTH
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embedded_system
Lab1 transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
71
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hereLEARN_IN DEPTH
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embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
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embedded_system
SPIh88
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hereLEARN_IN DEPTH
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embedded_system
SPIh89
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hereLEARN_IN DEPTH
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SPIc90
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hereLEARN_IN DEPTH
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embedded_system
SPIc
91
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hereLEARN_IN DEPTH
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
7-Segment Display
In many applications when you want to
display numbers 7-segments are the
best choice These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point
72
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemMAX7221 Interfacing and Proghellip
If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins This is not feasible
The MAX7221 IC is supports up to eight 7-segment LEDs We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs
The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes That means we do not need to refresh the 7-segment LEDs
All you need to do is to send a binary number to the MAX7221 and the chip decodes the binary data and displays the number
The device includes analog and digital brightness control an 8x8 static RAM that stores each digit and a test mode that forces all LEDs on
73
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Press
hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
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embedded_system
SPIc90
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hereLEARN_IN DEPTH
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embedded_system
SPIc
91
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hereLEARN_IN DEPTH
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs A resistor or a
potentiometer is the only
external component that you need
Next we will discuss the pins of
the MAX7221
GND Pin 4 and pin 9 are the ground These should be
connected to system ground
Vcc Pin 19 is the VCC and should be connected to the
+5Vthis pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA
74
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
ISET Pin 18 is ISET and sets the maximum
segment current This pin should be
connected to VCC through a resistor
A 10KΩ resistor can be connected to
this pin If you want to manually
control the intensity of the
segments light you can replace the
resistor with a 50KΩ potentiometer
CS Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR Serial
data is loaded into the chip while CS is low
and the last 16 bits of the serial data are
latched on CSs rising edge
75
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIN Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR On
CLKs rising edge data on this pin is loaded
into the internal shift register Notice that
the MAX7221 uses the SPI Mode 0 that is
read on rising edge and change on falling
edge
CLK Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR On MAX7221 the
clock input is inactive when CS is high
DOUT Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus
76
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 Pins and Connections
DIG0-DIG7
The DIG pins are the 7-segment selector pins and should be connected to the 7-segments common cathode pin The MAX7221 chip can control up to eight 7-segment LEDs These eight 7-segment dispalys are designated as DIGO to DIG7
SEGAhellipSEGG and DP These pins select each segment
and should be connected to segments of each 7-
segment accordingly
77
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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hereLEARN_IN DEPTH
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embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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embedded_system
SPIh88
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embedded_system
SPIh89
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embedded_system
SPIc90
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embedded_system
SPIc
91
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hereLEARN_IN DEPTH
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embedded_system
SPIc92
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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hereLEARN_IN DEPTH
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embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
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Follow us
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
In MAX7221 data packets are 16 bits long (two bytes) You should first make CS low before transmitting then you transmit two bytes of data and terminate the transmission by making CS high
The first byte (MSBs) of each packet contains the command control bits and the second byte is the data to be displayed
The upper four bits (D15-D12) of the command byte are dont care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed
The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver
Table 17-3 shows the binary and hex values of each command
78
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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hereLEARN_IN DEPTH
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embedded_system
MAX7221 data packet format
80
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
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embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
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embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
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embedded_system
SPIh88
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hereLEARN_IN DEPTH
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embedded_system
SPIh89
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hereLEARN_IN DEPTH
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embedded_system
SPIc90
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hereLEARN_IN DEPTH
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embedded_system
SPIc
91
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hereLEARN_IN DEPTH
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embedded_system
SPIc92
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format 79
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
MAX7221 data packet format
80
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system81
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to
send a sequence
Number to
Three 7-segment
82
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
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hereLEARN_IN DEPTH
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embedded_system
SPIh89
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hereLEARN_IN DEPTH
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embedded_system
SPIc90
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hereLEARN_IN DEPTH
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embedded_system
SPIc
91
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
SPI Master will increment counterAnd display the value on 7-segment 0 7-segment 1 and so on
83
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence Number to eight 7-segment
84
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
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Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_systemLab2 Use MAX7221 to send a sequence Number to eight 7-segment 85
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Lab2 Use MAX7221 to send a sequence
Number to eight 7-segment
Solution
86
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPI DriverHTTPSGITHUBCOMKEROLESEMBEDDED_SYSTEMTREEMASTERATMEGA32_DRIVERSATMEGA32_DRIVERSSPI
87
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh88
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIh89
httpswwwfacebookcomgroupsembeddedsystemKS
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hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
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embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
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Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc90
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc
91
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
SPIc92
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In your opinion What is the main
issue on this Driver
93
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
The main issue in this Driver isIf you configure the Driver to run as SPI Slave then the ldquoSPI_Send_And_recieverdquo API will hang the SW ldquoBlocking Coderdquo until the SPI master trigger a transaction
94
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
You can see we are using the C enum in the DriverWe can make all the SPI Configuration by using the macros instead of the enum
In your opinion
What makes a better constant in C a macro or an enum
95
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
Think in depth
In terms of readability enumerations make better constants than macros because related values are grouped together In addition enum defines a new type so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter
A macro is a preprocessor thing and the compiled code has no idea about the identifiers you create They have been already replaced by the preprocessor before the code hits the compiler An enum is a compile time entity and the compiled code retains full information about the symbol which is available in the debugger (and other tools)
Prefer enums (when you can)
96
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system
References
httpswwwnewbiehackcomMicrocontrollersABeginnersGuideIntroductionandInterfacinganLCDaspx
httpwwwslidesharenetMathivananNatarajanasynchronous-serial-data-communication-and-standards
httpswwwslidesharenetAnkitSingh13uart-32550652
the avr microcontroller and embedded System using assembly and c Muhammad Ali Mazidi
Embedded Systems lectures ldquoEngr Rashid Farid Chishtirdquo
httpswwwcoreliscomeducationSPI_Tutorialhtm
httpftmfutureelectronicscom201409nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems
httpwwwbyteparadigmcomproductsspi-stormspi-storm-advanced-information
httpsstackoverflowcomquestions17125505what-makes-a-better-constant-in-c-a-macro-or-an-enum
97
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
httpswwwfacebookcomgroupsembeddedsystemKS
Follow us
Press
hereLEARN_IN DEPTH
Be_professional_in
embedded_system98
