David Chapman Evan Kirkbride Bret Omsberg

Integrated Mixed­Signal Guitar Effects Chip 1. ABSTRACT

This project hopes to integrate typical guitar audio effects unto a single IC. Using analog amplifiers, filters, multiplexers, and digital control. The project also made use of a topology voltage controlled variable resistor made completely of mosfets [1]. The familiarization of VLSI design techniques acted as the main goal for this project, with bandpass filtering and op­amp design proving to be the most difficult. While improvement can be made in these areas, the techniques outlined in this project can apply to controllable analog design. 2. INTRODUCTION a. Background

There have existed guitar effects circuits since the 60s, but rarely are these hardware components integrated in a single chip. This project will focus specifically on the “wah” effect and distortion.

Historically, a wah effect consists of a bandpass filter that can potentially move the position of its center frequency and respective bandwidth. While there are many kinds of “wah” circuits, the most common is the traditional Vox, which is implemented with a couple amplifiers and an inductor (or equivalent). The distortion effect is usually implemented with a clipping amplifier. b. Highlights

Traditionally, wah and distortion effects are separate units and require discrete components; these products are not usually sold together or entirely integrated on a single chip. By packaging both effects on a single chip with a minimum of external components, the effects could directly built into a guitar instead of an external enclosure. Additionally, the use of digital controls will allow this chip to very precisely control the effects.

c. Projected personal growth

This project gives more insight into analog amplifiers and filters with the audio effects explored. It also includes digital control, allowing for a combination of digital and analog circuits. This allows for a broad spectrum of circuits for learning the processes and limitations of VLSI design. For example, this project will include the synthesis of large reactive components within the microscopic physical constraints of an IC. 3. DESIGN AND STEPS IN IMPLEMENTATION/INITIAL TESTING a. High­level description

Integrate two guitar audio effects into one integrated circuit. Both effects are analog but controlled with a digital system. The two effects are a “wah” with a moveable bandpass filter and

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a distortion effect with an amplifier. Two analog multiplexers allow the end­user to pick between a unmodified signal or any combination of the two effects. Analog voltages relative to VDD are input to the control lines, converted to digital, and used to control the effects and multiplexers. The control signals will control at a minimum the center frequency of the wah­wah and the gain (and thus amount of clipping) of the distortion. If there are sufficient I/O pads, additional control signals could be added that could control: the quality factor of the wah­wah, the output level of the circuit (ie add a linear amplifier to the output), or internal tone controls independent of the wah­wah. b. Big picture. Diagram of complete system.

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c. High­level block diagram

High level block diagram

d. Detailed block diagram For the wah effect, a moveable bandpass filter was required. To achieve this, an equivalent voltage controlled variable resistor was found in a paper by Kushima et al [1]. The layout of this resistor equivalent can be seen below.

Voltage Controlled Resistor

The use of this voltage controlled resistor (VCR) would be a simple way to move the

frequency range of a bandpass filter by changing the value of the resistances that set the 3 dB

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points. The VCR would be controlled with one control voltage signal, making it simple for the digital control to output with a DAC. This VCR is also only made up of MOSFETs, which makes the circuit easy to implement within an IC. Thus the basic block diagram for the wah circuit can be seen below.

Wah Effect Block Diagram

A high pass and low pass filter are cascaded with an amplifier buffering the two and

providing some gain. The VCR in each acts as a resistor and with its moveable value, the frequency range of the bandpass filter can change. The capacitors used may also be provided by external pins of the chip, if a large enough value is needed. The distortion circuit is an op­amp based amplifier that intentionally clips the audio signal. The amount of clipping is controlled by the amount of gain; more gain results in more clipping. The primary technical hurdle in implementing the clipping circuit was designing a suitable op­amp. Because the op­amp has applications in other portions of the circuit, the op­amp was designed to have a “rail­to­rail” output at the expense of current drive capability.

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Distortion Schematic

Op Amp Input Stages

The op­amp input stage consists of complementary differential pairs. Complementary pairs are used instead of a single PMOS or NMOS pair in order to take advantage of their respective output voltage ranges. The active loads are diode connected to increase gain. The loss of

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differential outputs that comes with diode connected loads does not matter as all stages except the input stage are single ended.

Op­amp input stage current sources

The current sources used for the input­stage differential pairs are based on the basic current mirror topology but with additional biasing circuitry. The net effect of this biasing circuitry is an increased compliance voltage over which the output current remains constant. Additionally, it

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allows a smaller biasing resistor to be used and results in less sensitivity to the actual value of the resistor.

Op­amp output stages

The op­amp output stages consist of two parts. The first stage combines the outputs of the complementary differential pairs into a single signal. The second output stage inverts the signal and additionally adds gain. The output stage can swing “rail­to­rail” when presented with small loads, reaching 100 mV of the positive rail and 50 mV of the negative rail. Because this system uses a single­sided power supply, a stable reference voltage at VDD/2 is needed for the amplifier biases. A resistive voltage­divider’s output would swing excessively due to loading so an active reference was designed. The design uses a voltage divider with equal resistances to generate an initial VDD/2 reference. This unbuffered reference is input into a voltage follower. The voltage follower consists of the rail­to­rail op­amp with an additional output buffer. The buffer limits the output swing, but that limitation does not matter as the reference ideally will only ever be at VDD/2. The simulation shows the reference’s output voltage and current as a function of load resistance. The reference has an error of less than 1.1% for resistances larger than approximately 40.5 kΩ. For for lower resistance loads, the output voltage drops; the output voltage is around VDD/4 for a load resistance of 2.5 kΩ.

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VDD/2 Reference schematic

VDD/2 reference output voltage and current as a function of load resistance

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Comparators to generate digital signal for Logic Gates

The circuit above shows two comparators used to generate two digital signals for Control1 and Control2 which are the two inputs to the logic gates. The comparator will output low for any C1 or C2 being less than VDD/6. This was achieved by using the voltage divider and inputting into the negative of the comparator.

Control Logic for Multiplexer select lines and transmission gate

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Control Signal Truth Table

Control1 Control2 M1 M2[1] M2[0] S1

0 0 X 0 0 0

0 1 0 0 1 1

1 0 1 1 1 1

1 1 1 0 1 1

The figure shown above shows how the select lines for the 2­to­1 and 4­to­1 multiplexers are generated from the control signals inputted into the integrated circuit. The source follower shown at the top of the image above is necessary due to low drive logic gates provide. A source follower will be implemented for each output signal in order to drive the switching of the multiplexers. The OR gate that generates the S1 output will be used to control if the transmission gate is closed or not.

Control Logic for Multiplexer Select Lines

Verilog Code for Control Logic Generation

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The combinational logic circuit that is shown above will be used to generate the select lines of the multiplexers used for signal selecting. The two control lines will be inputs to the integrated circuit and then passed through a comparator to generate the digital bits. An interesting thing about the synthesizer tool is that it will optimize the gates. This can be seen by looking at the verilog code and noting that an OR gate and an AND gate were used but in the design it generated a NAND gate and a NOR gate because it has less gates. The reason that this design was not used was due to the fact that the schematic cannot be carried over to Virtuoso for further design. If was a viable process, it would have the logic much easier to generate while still allowing for analog design in Virtuoso making the system much more robust as it could handle mixed signals in the same environment.

Analog­multiplexer block diagram

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Inverter Transistor Level Schematic

The inverter schematic shown above was used in designing both the AND and OR gates used in the rest of the control logic. The simulation for this circuit is shown below. The simulation shows that the input will always be the opposite of the output proving correct operation of the inverter.

Inverter Input/Output Simulation

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Voltage Divider and Comparator Schematic

Due to the two control signals being analog signals used for multiple different purposes, digital bits needed to be generated for the logic to work properly. This was originally designed to have a trigger point of VDD/6, or 0.3 Volts. When running the simulation for the comparator, the comparator would trigger 6% under the set point. This could be a problem if the integrated circuit was operating in a noisy environment. If the noise level reached over this trigger point, it could cause a whole range of issues. This was corrected by raising the trigger point to VDD/5, or 0.36 Volts. This would cause the trigger point of the comparator to be right around 0.3 Volts and would raise the ceiling for the noise level.

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And Gate Transistor Level Schematic

The first design process began in verilog. This was quickly scrapped when it was discovered that the design synthesized from the verilog code could not be altered in Virtuoso. This was a major design flaw for this design because it is a mixed signal chip, and there was no way to implement the comparator portion in Verilog. This was corrected by designing logic gates out of transistors and creating symbols for use in Virtuoso. The simulation shown below is the prove for operation of the AND gate. The two input signals are shown as the green and yellow signals. When one of these signals is low, the output shown in blue is low. Only when the two inputs are high will the output go high.

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And Gate Simulation

Or Gate Transistor Level Schematic

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The Or gate schematic shown above was designed using the nfetx and pfetx transistors. In addition to these transistors, an inverter shown as a rectangular block was also used. This last logic gate allowed for the entire control logic to be designed. The simulation shows the output over the entire truth table and proves proper operation. The output is shown in blue and is high whenever an input is high. This is shown below by only the first 10ms of the simulation is when the output is low because this is when both inputs are low.

Or Gate Simulation

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Control Logic Schematic

The full system shown above incorporates, op­amps, AND gates, or gates, inverters and resistors. This schematic utilizes the comparators discussed previously to generate the logic signals. Each symbol is labeled with the appropriate logic gate name. All of the blocks that are left unlabeled correspond to an op­amp that is either used as a comparator or a buffer. The buffer was utilized when a stronger current drive was necessary. This same function was implemented using a series of two inverters to up the drive to the rest of the system. If this was designed was to be optimized, the first thing that would be done would be to design the AND and OR gates as NAND and NOR gates. This would reduce the overall transistor count of the circuitry which would reduce the power consumption and the propagation delay of each gate. This is the main reason why the verilog code shown above inverted the logic that was inputted. The control logic symbol is shown below. The unique thing about this circuit is that it only takes two signals to generate ten different signals used to control transmission gates all around the circuit. Designing the control logic this way also saved a pin on the physical integrated circuit which is now used for an external capacitor.

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Control Logic Symbol

The input control signals, before reaching the comparators of the two effects’ controls were buffered with a simple op­amp voltage follower. The capacitor on the output eliminated the high­frequency oscillation that the op­amp produced in certain situations. Because the control signal varies slowly (at most 2 Hz) compared to the oscillation (~1 MHz) the capacitor does not affect the control signal.

Control­signal input­buffer

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e. Individual Circuits The wah was first simulated in LTSpice to verify its intent. A simple, ideal buffer was used in between the filters initially, as an op­amp had not been successfully designed by this point.

LTSpice Schematic

While varying Vbias (the control signal for the variable resistors) between 0 V and 1.8 V, the following plot was found.

Moveable Bandpass Functionality

As seen in the plot above, while the filter does not have ideal gain (which can be

remedied with a proper amplifier), its bandwidth is moveable and within values reasonable for the audio filtering required. However, once Vbias goes over a certain value, the transistor begin to work the integrity of the While the 1 fF capacitor for the high pass filter can be implemented in the IC, the 10 nF for the lowpass would need to have an external capacitor.

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Cadence Schematic of Voltage Controlled Variable Resistor

The functionality of the VDR was tested in Cadence with the schematic above. Vbias

was kept a constant value to keep a resistive value, and the voltage across the circuit was changed and the current through it was measured in ensure its resistive properties.

Resistance Test With Vbias = 0 V

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Resistance Test With Vbias = 1 V

Resistance Test With Vbias = 1.2 V

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Resistance Test With Vbias = 1.8 V

With these results, this implies that the lower the Vbias, the lower the resistive value.

However, at higher Vbias values, such as when Vbias=1.8 V, the circuit stops acting as an ideal resistor with a linear voltage/current relationship.

With the resistive relationship confirmed, the VCR was given a component symbol, and used with a capacitor to confirm its low pass filter functionality. This was done with the schematic below.

Low Pass Filter Test Circuit

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With the Vbias value being set to different values, and with the capacitor being made as large as cadence will allow (about 2pF), the following AC responses were found.

Low Pass AC Response with Vbias=0.8 V, Large Capacitor

Low Pass AC Response with Vbias=1V, Large Capacitor

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Low Pass AC Response with Vbias=0.4 V, Large Capacitor

The 3 dB point for each of the plots above is in the 10 kHz range, despite the large capacitance. This implies than an even larger capacitance will be needed in order to get the 3 dB point at a workable 1kHz range, implying the need for an external capacitor in the nF range. For a functionality test, a smaller sized capacitor (fF range) was tested was also tested with this setup.

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Low Pass AC Response, Vbias=0.4 V, Small Capacitance

Low Pass AC Response, Vbias=1 V, Small Capacitance

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With a small capacitance, the functionality of a low pass filter is destroyed. Giving more

of a reason for a larger capacitance. The high pass filter response was tested with a similar method, resulting in the

schematic and AC responses seen below.

High Pass Filter Schematic

High Pass Filter AC Response with Vbias=1 V

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High Pass Filter AC Response with Vbias=1.8 V

Despite the large capacitance and range of Vbias and resistive values used above, the 3

dB point stayed within the kHz to MHz range, more than the required range around 300 Hz. This also implies the need of an external, larger capacitance. Nonetheless the functionality of the variable filtering capabilities were confirmed. All that’s needed is some gain, as well perhaps a higher Q factor.

The low pass filter was improved upon by stacking resistors and capacitors as seen below.

Stacked LP Filter

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The thought process of the above circuit is that if ω=1/RC, increasing R and C will decrease the cut­off frequency to something workable in the audio range. Simulating this circuit resulted in the AC responses below.

Stacked LP Filter Plot: Vbias=0.2 V, f3dB=3.25 MHz

Stacked LP Filter Plot: Vbias=1.6 V, f3dB=25 kHz

From the plots above, while the tunable bandwidth reaching 3.25 MHz, the filter can still reach 25 kHz, which is closer to the audio spectrum at 20 kHz. However, the 3 stacked VCR’s who all

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range their value end up giving this large tunable bandwidth. To counteract this, the circuit below was built.

Stacked Resistors LP Filter

The circuit above uses 4 resistors in series before two VCR’s, this f3dB point will be more fixed if only ⅓ of the resistors are tunable. Simulating these circuits resulted in the following plots.

Stacked Resistors LP Filter Plot: Vbias=0.2 V, f3dB=40 kHz

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Stacked Resistors LP Filter Plot: Vbias=1.6 V, f3dB=20 kHz

Stacked Resistors LP Filter Plot: Vbias=1.8V, f3dB=700 Hz

The plots above illustrate 3dB points between 20 kHz and 700 Hz, which is within the audio spectrum. However, the Vbias has only a 0.2 V range to achieve these bandwidths. This implies that gaining a moveable bandpass in the audio spectrum equivalent to a wah effect, however multiple stacked resistors and capacitors will be required, which will eat up space on the IC.

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These filters also do not have a reasonable Q factor for a wah effect. to account for this, a Sallen­Key Filter was implemented.

Initial Sallen­Key Circuit

The circuit above used relatively small resistor and capacitor values, to simply test the effectiveness of the circuit. With this, the following plots were found.

Initial Sallen­Key Plot, Vbias=1 V

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Initial Sallen­Key Plot, Vbias=1.8 V

With the Sallen­Key, though the Q factor improved, the gain and center frequency (which is in the MHz range) did not. To prevent this, staked resistors and capacitors were used with the Sallen­Key as seen below.

Improved Sallen Key Circuit

The circuit above resulted in the simulations below.

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Improved Sallen­Key Plot

While the center frequency above is improved (though still not within the audio spectrum). The Q factor and gain is not that much improved. This implies that while a good wah­effect could possibly be achieved with a Sallen­Key, simply raising the components may not be a viable solution, and a more nuanced balance of components is needed. Lastly, the use of an external capacitor was considered by using the analog library in cadence. Using an external capacitor in conjunction with a Sallen Key bandpass filter [2] allowed for a high Q factor required for a Wah effect, and for a frequency range low enough for the sound spectrum. After some trial and error, the final Wah effect filter used the topology below.

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Finished Wah Effect Circuit

In comparison with the base topology below, the VCR’s make up R1, Rf, and R2, along with some stacked resistors to help push the bandwidth down to the sound frequency range. C1 acts as an external cap of 10 nF, and C2 is an on­chip capacitor made as big as an pcdcapx in cadence is allowed. The op­amp above acts as a voltage follower instead of the non­inverting amplifier below, as attempting to create a gain with the op­amp used proved to be difficult. For example the push­pull output stage after the op­amp is required as the op­amp cannot drive or be loaded with much.

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Basic Sallen­Key Bandpass Topology The frequency of responses of the Wah­effect at different Vbias values, demonstrating a moveable bandpass filter can be seen below.

Wah­Effect Frequency Response: Vbias = 0 V

Wah­Effect Frequency Response: Vbias = 0.9 V

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Wah­Effect Frequency Response: Vbias = 1.6 V

The op­amp was first tested in an open loop configuration to verify that the differential gain was large. After the differential gain was verified, the op­amp was tested with various closed loop configurations. The voltage range of the unloaded amplifier is shown below, with the op­amp operating as a unity gain voltage follower. The output is within 100 mV of the positive rail and 50 mV of the negative rail.

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Unloaded op­amp voltage follower

With a 366 kΩ load, the voltage follower performs identically to the unloaded case. High loads, though, dramatically reduce performance. With a 100 kΩ, the maximum output drops to 250 mV of the positive rail.

Voltage follower with 366 kΩ load

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Voltage follower with 100 kΩ load

The op­amp also successfully can drive large loads when it is configured to have a greater­than­unity gain. The following transient simulation shows the input and output of a non­inverting amplifier constructed with the op­amp driving a 230 kΩ load.The output ranges from 50 mV to 1.75 V for a peak­to­peak voltage of 1.7 V. This output is 5 times larger than the input of 340 mVpp, demonstrating the op­amp’s correct operation.

Noninverting amplifier with a gain of 5 and a load of 230 kΩ

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The distortion circuit was tested by applying a sinusoid to the input and monitoring the output voltage. The simulation shows hard clipping, as expected. However, after around 9.5 ms, a 500 MHz oscillation begins occur. The oscillation is not correlated to the input frequency, making this circuit unsuitable for implementation.This issue was not ultimately resolved as the aim of this project was to be educational.

Distortion transient simulation

Distortion transient­simulation oscillation detail

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The input buffer was tested by sweeping the input and measuring the buffer’s output voltage. A comparator and VCR were used as typical loads. A transient simulation was performed to verify that unwanted high­frequency oscillations did not occur.

Input buffer test setup

Input buffer and VCR resistance. The redline is the input voltage and the green line is the

buffered voltage. The blue line is proportional to the VCR resistance. The buffer performs well with the small load presented by the comparator and VCR, deviating by 50 mV at the bottom of the range and 100 mV at the top of the range. The transient simulation also showed that no unwanted oscillations occurred.

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f. Full design The signal distribution network, consisting of the digital controls, multiplexors, and single transmission gate was first tested without any of the effects. Simulator stimuli were used in place of the effects’ outputs.

Signal routing test schematic

Signal routing test results

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Complete system integration

Complete system integration with IO pads and corners

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4. Final System The final layout easily fit onto the the 0.9 by 0.9 mm die as no large internal capacitors were used. Around 50 warnings were produced but no errors.

Laid­out system

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The input comparators, used to select the signal pathway, ended up­grouped together. The resistive divider which sets the trigger level is on the left side. Each set of resistor pairs and associated transistors is an op­amp. Two of the op­amps are used as comparators and the third is used as a buffer.

Input comparators

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The input control signal buffers also were grouped together in a recognizable fashion. Each buffer consists of an op­amp and capacitor, with each op­amp consisting of a resistor pair and transistors.

Input Buffers

It is interesting to note that the automatic layout tool structured the op­amps used in the comparators far differently than it did for the input buffers. Most of the transistors in the comparators were placed in between the resistor pair while none of the transistors in the buffer op­amps were placed in between the resistors. 5. Analysis of Results and Conclusion

This project allowed for an adequate introduction of the constraints and concerns of VLSI design. More variables need to be considered than traditional circuit design, such as physical component size and what maximum nominal values are allowed. This proved especially problematic in the wah­effect design, which required large values for low­frequency filtering. The eventual simulations for the wah­effect showcase decent frequencies, but still required the addition of an external capacitor. The gain of the filter was also much less than ideal, likely caused by the op­amp used, which proved unable to create a steady gain with the addition of resistors. The other components, however, proved much more effectful in simulations. Digital control was originally done with Verilog for the initial design, however simulations needed to be done by hand. The distortion effect used an op­amp that intentionally clipped, which, even for the op­amp used, proved adequate. The digital control and distortion were able to prove their functions when integrated and simulated together, however the wah­effect still only barely functions as a filter.

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The obvious improvements would be to correct the wah­effect and op­amp. The design can also be expanded by adding more effects to the chips, as the was space left after the addition of the I/O pads and corners. The additional space could be also used for larger transistors, increasing the op­amp’s drive capability. The space could also be used for more complex layouts, including a common centroid layout for the op­amp differential­pair transistors, which could reduce the effect that manufacturing variability has on this system. An extra pin is also available for a control input to allow for extra effects. The constraints of VLSI design should be taken more into consideration if these ideas are implemented in the future, to prevent the shortcomings of the project thus far. 6. Appendix

a. Who did what part of the project The initial plan is to divide up the design into three parts: the digital controls, the wah, and the distortion+multiplexers. Each subsystem should have a similar amount of design work.

Bret: Controls David: Distortion + Multiplexers Evan: The Wah Effect

[1] Kushima et al, “Design of a floating node Voltage­Controlled Linear Variable Resistor” The 47h IEEE International Midwest Symposium on Circuits and Systems, 2004. pp. I­85 ­ I­88. gdsii file path: /homeF15/dnchapma/integrated_system.gds.gz

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