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FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY An overview of modern digital electronic design Angel Salas Mechatronics Engineer

FPGA Overview

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Page 1: FPGA Overview

FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY

An overview of modern digital electronic design

Angel SalasMechatronics Engineer

Page 2: FPGA Overview

What is an FPGA? Reprogrammable silicon

chip, choosing prebuilt logic blocks and programmable routing. Create personalized hardware without proto-board, chips & wiring.

Hardware-timed speed up to 25 ns response and high reliability in processing.

Can implement a Soft Core processor embedded.

Parallel nature: Each processing task is assigned to a specific section of the chip and functions autonomously from other processing operations. Angel A. Salas Mechatronics Engineer

Page 3: FPGA Overview

Angel A. Salas Mechatronics Engineer

True ParallelismExample: Having 6 PWM working simultaneously with different frequency and variation of the duty cycle in each cycle.

Page 4: FPGA Overview

Overall architecture The fabric of a basic

FPGA contains: input/output blocks, a sea of programmable routing wires, islands of logic blocks and memory blocks.

More sophisticated includes: digital signal processing, MB chip-on memory, high-speed serial interconnect transceiver, phase-locked loop and other functions. Angel A. Salas Mechatronics Engineer

Page 5: FPGA Overview

Angel A. Salas Mechatronics Engineer

Internal architecture

Page 6: FPGA Overview

Angel A. Salas Mechatronics Engineer

Configurable Logic Blocks (CLBs)

* Contain the slices: SLICEM (memory), SLICEL (logic).

• Look-up Tables (LUT) which implement logic functions truth table

*Carry and Control LogicImplements fast arithmetic

operations (++/ --)Configured for additional

operations (Built-in-Self Test iterative-OR chain)

*Memory ElementsConfigurable Flip Flops (FFs)/

Latches( Programmable clock edges, set/reset, and clock enable)

These memory elements can be configured as shift-registers

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

Page 7: FPGA Overview

Angel A. Salas Mechatronics Engineer

Look Up Table (LUT)

Can be configured to represent whatever logical function.

Uses memory to program output truth table

Page 8: FPGA Overview

How to program it

•Needs Hardware Description Language code (Firmware).•Hardware implementation designed like software.•Verification & validation: reviews, simulations & test.•IDE (integrated development environment)

Different types of coding: VHDL, VERILOG, SYSTEM VERILOG, HANDEL-C, LabVIEW, MatLab.

Page 9: FPGA Overview

Angel A. Salas Mechatronics Engineer

Hardware Description Language

Describe functions Abstraction level is

on Register Transfer Level

Uses variables, parameters & subroutines

Code ‘executes’ in parallel with separate hardware

VHDL (very high speed integrated circuit HDL)

Verilog.

Page 10: FPGA Overview

High Level Synthesis G-Language LabVIEW Represents

parallelism & dataflow

Can integrate IP VHDL code into the graphic design

Test benches and depurations implemented graphically

Interactive mode with PC

Page 11: FPGA Overview

Angel A. Salas Mechatronics Engineer

FPGA Implementation Examples

Phase Shifted PWM Multilevel three-phase inverter for wind turbine generator

7 PSPWM levels 18 PWM simultaneous Phase shift controller Carrier modulation signal Interface to PC to modify parameters on the run

Page 12: FPGA Overview

Angel A. Salas Mechatronics Engineer

DNA chip and AG for mobile robot

Parallel operations of hundreds of Genes Path planning Rule evaluation according with matching Genetic Algorithm applied to the “learning” of the

system

Page 13: FPGA Overview

Angel A. Salas Mechatronics Engineer

Artificial Vision in Robotics

Feature Density & Distribution Algorithm Principal Component Analysis Stereo vision & motion analysis to discover depth away Sum of Absolute Differences Algorithm Path tracking for moving objects

Page 14: FPGA Overview

Angel A. Salas Mechatronics Engineer

Advantages of FPGA technology

MAINTENANCE. FPGA chips can keep up with future modifications that might be necessary. Functional enhancements can be made without spending time redesigning hardware or modifying the board layout. 

RELIABLILITY. Processor-based systems often involve several layers of abstraction to help schedule tasks and share resources among multiple processes. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks preempting one another. FPGAs, which do not use OSs, minimize reliability concerns with true parallel execution and deterministic hardware dedicated to every task.

PERFORMANCE. FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. Controlling inputs and outputs (I/O) at the hardware level provides faster response times and specialized functionality to closely match application requirements.

Page 15: FPGA Overview

Angel A. Salas Mechatronics Engineer

Summary

FPGA is a flexible hardware device adaptable to different needs.

Parallel processing of data High speed processing Useful for prototyping & research in

various fields Able to have embedded cores

Page 16: FPGA Overview

Angel A. Salas Mechatronics Engineer

Questions session


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