Mini Project2

Lakshmi Yasaswi Kamireddy

651771619

Graduate Student

Problem Description:

The purpose of this project is to design and simulate a negative edge triggered D register in the standard 0.25u CMOS technology. This project mainly focusses on minimizing the propagation delay and the area.

Design:

There are many ways of designing a register using either static or dynamic latches as the master and slave. Figure 1 shows the configuration of a master slave configuration of negative edge triggered D register. It is a combination of positive D latch as master and a negative D latch as slave.

Figure 1

Now these two latches can be designed using either static or dynamic latches. In this project two implementations are done .The first one is static nmos only negative edge triggered D register and the other is dynamic nmos only negative edge triggered D register. Figure 2 and 3 show the configurations.

Figure 2

Figure 3

After the simulation has been performed it has been observed that the static type has produced less propagation delay compared to the dynamic type. Initially when thought about it was contradictory to what we think because we know that dynamic circuits are faster compared to static circuits. If you can see the D has to pass through only one transistor and one inverter per latch in dynamic where as it has to pass through one transistor and two inverters in static. But this alone will not make it faster because we should also consider the time taken for the capacitor to charge is also important. It cannot be small because it should maintain the input voltage values to the inverter that obey the noise margins. Otherwise the circuit functionality will be correct. For (W/L) =1 of the nmos (connected to clock and ~clock) will have higher precharge time in the dynamic gate due to high resistance .This precharge time can be reduced by increasing the (W/L) will help in reducing the precharge time and hence the overall propagation delay. In our case even with a sizing of (W/L)=4 for the dynamic type it was not good enough compared to the static gate. The values for the propagation delays obtained from the simulations have been listed in the results section. So, static type proved better for propagation delay.

To optimize area the designed was made as compact as possible following the DRC rules. Though dynamic type has less area we go for static design as the primary objective was to reduce the propagation delay.

Schematic:

Schematic for Static nmos only type:

Figure 4

Schematic for Dynamic nmos only type:

Figure 5

Schematic for test:

Figure 6

Layout of Static CMOS: (same for test and the original circuit):

Figure 7

Extracted layout for test (same for test and the original circuit):

Figure 8

Analog extracted (same for test and the original circuit):

Figure 9

Results:

DRC check for layout:

Figure 10

LVS pass for the schematic and layout of the original circuit:

Figure 11

LVS pass for test schematic:

Figure 12

Simulated output for dynamic type with (W/L=1 fornmos transistor connected to clk and ~clk)

Figure 13

The total propagation delay will be the time for input to change plus the rise time in both these cases. For (W/L)=1 it will be 2.235ns+precharge time1. For (W/L)=4 it will be 1.568+precharge time2. Note that precharge time 1>precharge time 2 because grater the sizing lower will be the resistance and hence less delay.There will be a tradeoff point where capacitance starts dominating and it will increase the delay as the sizing increases. But anyway as we are going for static a much detailed analysis is not done in this case.

Simulated output for dynamic type with (W/L=4 for nmos transistor connected to clk and ~clk)

Figure 14

There is a very high

precharge time, after

the occurrence of the

negative edge it takes

long for the output to

turn to 1

There is a very high

precharge time, after

the occurrence of the

negative edge it takes

less time than (W/L)=1

for the output to turn

to 1

Simulated output for static with no parasitic capacitances

Figure 15

If observed there is no extra precharge time because of the capacitor. The output will be changed after the contamination delay. So the total propagation time will be almost equal to the rise time. The value is 0.25ns.

Parasitic capacitances:

Figure 16

Simulated output for static with parasitic capacitances

With parasitic capacitances the delay is 0.32ns.

Figure 17

Conclusions:

The negative edge triggered D register is implemented successfully to reduce propagation delay and area. For this the static type proved to be better than dynamic type in terms of delay .The area minimization was obtained by following Design rules carefully. The design passed LVS and DRC successfully. The parasitic capacitances were also calculated using the Build Analog option. Post layout simulation was performed successfully.The design showed an increase in propagation delay from 0.25ns to 0.32ns when simulated with parasitic capacitances.