DESIGN OF SIMULATION DIFFERENT 8-BIT MULTIPLIERS USING

VERILOG CODE

ABSTRACT:

Low power consumption and smaller area are some of the most important criteria for

the fabrication of DSP systems and high performance systems. Optimizing the

speed(reducing propagation delay time) and area of the multiplier is a major design issue.

However, area and speed are usually conflicting constraints so that improving speed results

mostly in larger areas. In our project we try to determine the best solution to this problem by

comparing a few multipliers.

This project presents an efficient simulation and implementation of high speed 8-bit

multipliers using the VERILOG code. In this project we compare the working of the four 8-

bit multipliers like Wallace tree multiplier, Array multiplier, Baugh wooley multiplier and

Vedic multiplier by simulation. This is a very important criterion because in the fabrication of

chips and high performance system requires components which are as small as possible.

.

In our project when we compare the power consumption of all the multipliers we find

that Wallace tree multipliers consume more power. So where power is an important criterion

there we should prefer another multiplier like array multiplier. The low power consumption

quality of array multiplier makes it a preferred choice in designing different circuits.

In this project we first designed four different types of multipliers using VERILOG

code. We used different types of adders like half adders and full adders in designing these

multipliers. Then we compared the working of different multipliers by comparing the power

consumption by each of them. The result of our project helps us to choose a better option in

fabricating of different systems. Multipliers form one of the most important components of

many systems. So by analyzing the working of different multipliers helps to frame a better

system with less power consumption and lesser area.

BLOCK DIAGRAMS:

LANGUAGE USED:VERILOG

SOFTWARE TOOLS REQUIRED:Simulation: Xilinx ISE 14.7

Synthesis: Xilinx ISE 14.7

HARDWARE TOOLS REQUIRED:Implementation: FPGA (Field Programmable Gate Array)

ADAVANTAGES:1. Reduced wire length.

2. High clock rate.

3. Small area.

4. Low power consumption

5. Increasing speed.

DISADAVANTAGES:1. Reducing delay needs additional circuitry which increases area so that power

dissipation also increases.

2. Complexity of the circuit increases to reduce the critical path of the propagation delay

time.

APPLICATIONS:Multipliers are employed in various digital signal processing operations such as

convolution, correlations, frequency analysis and filtering.

Guide ByS.BALAIAH M.Tech., (Ph.D) P. SAIKIRAN (12631A0469)

Associate Professor. M. SOUJANYA (12631A0488)

S. VEERANNA (12631A04A7)

N. SRINATH (12631A0496)