Presentation On

Cutset Retiming Presented By:Saurav Agrawal

Priyadarshini College of Engineering, Nagpur

Department of Electronics and Telecommunication Engineering

Retiming

• A technique used to change the location of delay in a circuit.

• It maps the circuit G to retimed circuit Gr

• Retimed weight wr(e)is given by wr(e)=w(e)+r(V)-r(U)

1

Cutset Retiming• A retiming technique used for retiming.

• A cutset is a set of edges that can be removed from the Graph.

• It only affects the weight of the edges.

• Consist of 3 cases: 1) Case 12) Case 23) Case 3

2

2D

Case 1

fig(i) Original DFG fig(ii)A DFG with cutset

1

4

32

DD

1

4

32

DD

2D

3

• The 2 disconnected subgraphs are labeled G1 and G2

4

2

1

3

G1

G2

•Add k delays to each edge from G1 to G2 •Remove k delays from each node from G2 to G1

4

• Let k=1 Then the Retimed DFG Gris

1

4

32

DD

3D

5

Case 2

• A cutset is chosen so the subgraph G2 is a single node and the subgraph G1 is the rest of the graph.

Original DFG DFG with a cutset

1

4

32

DD

2D

1

4

32

DD

2D

6

G1G2

• Subgraph G2 is a single node subgraph consisting node 2 and the subgraph G1 consist of the rest of the graph

2

1

4

3

D2D

•Add k delays to each node incident into node 2•Subtract k delay from each node outgoing from node 2

7

• Let k=1 Then the Retimed DFG Gr is

1

4

32

D

D2D

8

Case 3

• Pipelining is a special case of cutset retiming

Original pipelined DFG DFG with Cutset

OUT

INdd

cba x x x

+ +

x x

+ + OUT

INdd

cba x

9

• All 3 edges in the cutset go from G1 to G2 and perform cutset retiming

G2

G1

OUT

ddIN

x x xcba

+ +

•This pipelining retiming results in adding k delays on each edge from G1 to G2

10

2D 2D2D

• Let k=2 delays Then the Retimed DFG Gr is

OUT

INdd

cba x x x

+ +

11

13

References

• Leiserson, 1C. E.; Saxe, J. B. (1983). "Optimizing Synchronous Systems". Journal of VLSI and Computer Systems 1 (1): 41–67.

• http://citeseer.ist.psu.edu/context/96547/0• Jump up^ C. E. Leiserson, J. B. Saxe, "Retiming

Synchronous Circuitry," Algorithmica, Vol. 6, No. 1, pp. 5-35, 1991.

• ^ Jump up to:a b K. N. Lalgudi, M. C. Papaefthymiou, Retiming edge-triggered circuits under general delay models, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, no.12, pp.1393-1408, Dec. 1997.

THANK YOU