5.2. lithography 3,4,5 final,2013

Microelectronics Technology:

Photolithography

(Mask Engineering,Manufacturing Methods & Process Modeling)

Photoresist Exposure: Issues

Ideal Aerial Imag

Exposing Light

• There are often a number of additional issues that arise in exposing resist.

• Resist is applied as a liquid and hence "flows" to fill in the topography.

• Resist thickness may vary across the wafer. This can lead to under or over exposure in some regions and hence linewidth variations.

Photoresist Exposure:IssuesPlanarization Layer Etch Mask layer Imaging Layer

• Multi-layer resists are used to produce a thin, uniform imaging layer in which the aerial image is transformed into a latent image.

• Etching is then used to transfer the latent image down through the planarization layer.

Photoresist Exposure: IssuesAerial Image Exposing Light

• Reflective surfaces below the resist can set up reflections and standing waves and degrade resolution.

• In some cases an antireflective coating (ARC) can help to minimize these effects. Baking the resist after exposure, but before development can also help.

MASK FABRICATION: TECHNIQUES

TYPES OF SUBSTRATE

1. Quartz - Ultra Low Thermal Expansion (ULTE)2. Borosilicate Glass – Low Expansion3. Soda Lime Glass - Economical Substrate Typical Properties

Properties Quartz Borosilicate Glass

Soda Lime

Glass Thermal Exp. Coefficient 5.2x10-

7

37x10-7 94x10-7

Refractive Index 1.47 1.53 1.52

Light Transmittance (%) 436 nm 200 nm

9070

90--

90--

Electrical Resistivity (-cm)

1018 1015 1012

Coating for Mask Blanks

• Photo Emulsion (Silver Halide based) • Chromium (Cr)• Chromium Oxide (Cr2Ox)• Iron Oxide (Fe2O3)• Silicon (Si) • Photo Sensitive Resists

Emulsion Vs Chrome

Type Advantages Disadvantages

Emulsion Low CostHigh Photo-sensitivity Easy Processing Good Image Resolution and ContrastEasy Reversal Processing

Tender and Scratch SensitiveLife is Shorter

Chrome Hard Surface CoatingLonger LifeSharp EdgesEasy Mask Cleaning

High Reflectivity

Mask Parameters

• Type of Substrate • Size of Mask Plate • Required Field • Scale Factor/Data Magnification• Image Mirroring/Rotation• Input Data Format (CIF, GDSII, DXF, GURBER…)• Layer ID, Total Number of Layers & Layer Title

Mask Specification: • Minimum Feature Size • Total Area of Design • Step & Repeat -- Array & Stepping Distance

Lay-out PlanningFactors to be considered

• For which Aligner / Stepper the Masks are to be Prepared

Fiducials (if Required for Step & Repeat) Wafer Alignment Marks CD (Critical Dimensions) Structures Layers / Product Identification Marks Dicing Requirements (i) Minimum Scribe Width (ii) Step Size Constraints

Processing

Emulsion Plates

Developing Fixing Water Rinsing

Chrome Plates

Developing Etching Photo Resist Stripping Water Rinsing Cleaning

Mask Quality Inspection

• Visual Inspection

• Measurement

D: Mask Engineering – OPC and Phase Shifting




Manufacturing Methods and Equipments

30


Conceptual diagram of a scanning projection printer



On-axis Illumination



• This further decreases the optical “window” and therefore makes it possible to build higher performance optical systems over a smaller area.

• The most recent “steppers” are step and scan systems.

Electron Beam Lithography

• Process of scanning a beam of electrons in a patterned fashion across a surface covered with a electron resist.

Electron Beam Lithography System

• Electron Gun or Electron Source

• Electron Column

• Mechanical Stage

• Wafer Handling System

• Computer System

Electron Optical System

Electron gun Alignment coil

First condenser lens

Blanking plates

Second condenser lens

Limiting aperture

Final lens, coils

Electron resists Substrate Mechanical stage

EB Writing Scheme: Raster Scan

Vector Scan

Electron Beam Lithography

• Advantages• Better Resolution

• Disadvantages• Low Throughput• High Cost

Models and Simulation

• Lithography simulation relies on models from two fields of

science:

• Optics to model the formation of the aerial image.

– Water Exposure System Models

• Chemistry to model the formation of the latent image in the

resist.

– Optical Intensity Pattern in the Resist

– Photoresist Exposure

– Photoresist Baking

– Photoresist Developing

A: Wafer Exposure System Models






ExampleConsider a long rectangular slit. The Fourier transform of t(x) is in standard texts and is sin(x)/x function.




Colors correspond to optical intensity in the aerial image. Exposure system: NA = 0.43, partially coherent g-line illumination ( = 436 nm). No aberrations or defocusing. Minimum feature size is 1 µm.

• ATHENA simulator (Silvaco).


• Same example as previous except that the feature size has been reduced to 0.5 µm. Note the poorer image.


• Same example as previous except that the illuminationwavelength has now been changed to i-line illumination ( = 365

nm) and the NA has been increased to 0.5. Note the improved image.

B: Optical Intensity Pattern in the Resist



• Example of calculation of light intensity distribution in a photoresist layer during exposure using the ATHENA simulator. A simple structure is defined with a photoresist layer covering a silicon substrate which has two flat regions and a sloped sidewall.

The simulation shows the [PAC] calculated concentration after an exposure of 200 mJ cm-2. Lower [PAC] values correspond to more exposure. The color contours thus correspond to the integrated light intensity from the exposure.

C: Photoresist Exposure


dz



D: Photoresist Baking

D: Photoresist Baking

• Same simulation example as last one except that a post exposure bake of 45 minutes at 115 °C has now been included. The color contours again correspond to the [PAC] after exposure. Note that the standing wave effects apparent earlier have been “smeared out” by this bake, producing a more uniform [PAC] distribution.

E: Photoresist Developing



• Example of the calculation of a developed photoresist layer using the ATHENA simulator. The resist was exposed with a dose of 200 mJ cm-2, a post exposure bake of 45 min at 115 °C was used and the pattern was developed for a time of 60 seconds, all normal parameters. The Dill development model was used.


Way through development. Complete development.

Future Trends

• Optical lithography has been extended to the 100 nm generation and it may be extendible up to 70 / 50 nm features.

• Beyond that, there is no general agreement on which approach will work in manufacturing.

• Possibilities include e-beam, e-beam projection, X-ray and EUV.

• New resists will likely be required for these systems.

Summary of Key Ideas

• Lithography is the key pacing item for developing new technology generations.

• Exposure tools today generally use projection optics with diffraction limited performance.

• g and i-line resists are based on DNQ materials and are used down to 0.35 µm dimensions.

• DUV resists use chemical amplification and are generally used for smaller feature sizes.

Summary of Key Ideas

• Lithography simulation tools are based on Fourier optics and do an excellent job of simulating optical system performance. Thus aerial images can be accurately calculated.

• Photoresist modeling (exposure, development, postbake) is less advanced because chemistry is involved which is not as well understood. Thus latent images are less accurately calculated today.

• A new approach to lithography may be required in the next few years.

Photo Resist Spin Coating, Mask Inspection, Wafer & Mask Alignment


This is the photograph of a step and scan projection aligner (Canon FPA-4000ES1). This system is capable of printing 0.25 µm features with a throughput of 80 8” wafers per hour. With 4X reduction, the field size is 25 x 33 mm. It has an alignment capability of ±70 nm. The NA is 0.63 and the illumination source is a KrF excimer laser ( = 248 nm). The system uses an advanced off-axis partially coherent illumination system.

Electron Beam Lithography System

• The most recent “steppers” are step and scan systems.

(Photo taken directly from the Canon website at http://www.usa.canon.com.)

http://www.usa.canon.com/