UGC NET Computer Science Test

Computer Science - Computer Science Test - ComputerOrganisation & Architecture - COA Online Test 1

No. Question

1 A low memory can be connected to microprocessor by using

A INTER B RESET IN

C Both (a) and (b) D READY

2 A basic instruction that can be interpreted by a computer generally has

A An operand and an address B A decoder and an accumulator

C Sequence register and decoder D None of these

3 The addressing mode used in an instruction of the form ADD X, Y, is

A absolute B immediate

C indirect D Relative

4 Number of machine cycles required for RET instruction in 8085 microprocessor is

A 1 B 2

C 3 D None of these

5 The 8085 microprocessor responds to the presence of an interrupt

A As soon as the TRAP pin becomes 'LOW' B By checking the TRAP pin for 'high' status

at the end of each instruction fetch

C By checking the TRAP pin for 'high' status at the

end of the execution of each instruction

D By Checking the TRAP pin for 'high' status

at regular intervals

6 The TRAP interrupt mechanism of the 8085 microposser executes

A An RST by hardware B The instruction supplied by external device through the

INTA signal

C An instruction from memory

location 20 H

D None of these

7 The address range to which I/O chip will respond is

A 0000 H to FFFF H B 0000 H to 5FFF H

C 4000 H to 5FFFF H D None of these

8 What is the average access time for a drum rotating at 4000 revolutions per minute?

A 2.5 milli seconds B 5.0 milli seconds

C 7.5 milli seconds D 10.0 mili seconds

9 What is the byte capacity of a drum which is 5 inch high, 10 inch diameter, and which has 60

tracks per inch bit density of 800 bits per inch ?

A 94200 bytes B 471000 bytes

C 18840 bytes D 16384 bytes

10 The memory address range to which RAM will respond

A 0000 H to 1 FFF H B 0000 H to 5FFF H

C 4000 H to 5FFF H D 3000 H to FFFF H

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UGC NET Computer Science Practice Test 1

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11 Which of the following is not a form of memory ?

A Instruction cache B Instruction register

C Instruction opcode D Both (a) and (b)

12 Desirable characteristic(s) of a memory system is(are)

A Speed and reliability B Low power consumption

C Durability and compactness D All of these

13 For a memory system, the cycle time is

A Same as the access time B Longer than the access time

C Shorter than the access time D multiple of the access time

14 In comparison with static RAM memory, the dynamic RAM memory has

A Lower bit density and higher power

consumption

B Higher bit density and low power

consumption

C Lower bit density and lower power

consumption

D None of these

15 The access time of magnetic bubble memory is approximately

A 30 nano seconds B 30 micro seconds

C 30 pico seconds D 0.3 seconds

16 Memory refreshing may be done

A By the CPU that contains a special refresh counter,

only

B By an external refresh controller,

only

C Either by the CPU or by an external refresh controller D None of these

17 A dynamic RAM consists of

A 6 transistors B 2 transistors and 2 capacitors

C 1 transistor and 1 capacitor D None of these

18 Match List I with List II and select the correct answer form the codes given below the list.

List I A. An 8-bit wide 5 word sequential memory will have B. A 256 x 4 EPROM has List II

1. 8 Fixed 'AND' gates and 4 programmable OR' gate 2. Eight 4 bit shift registers 3. 4 words

of 32-bits each 4. 8 address pins and 4 data pins output CODES: A B

A 1 2 B 3 2

C 2 3 D 4 2

19 In a virtual memory system the address space specified by the address lines of the CPU must

be -----------than the physical memory size and -----------than the secondary storage size.

A smaller, smaller B smaller, larger

C larger, smaller D larger, larger

20 Which of the following is/are advantages of virtual memory ?

A Faster access to memory on an average. B Processes can be given protected

address spaces.

C Programms larger than the physical memory size

can be run.

D All of these

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21 Property of locality of reference may fail, if a program has

A Many conditional jumps B Many unconditional jumps

C Many operands D Many Operators

22 How many RAM chips of size (256K x 1 bit) are required to build 1M Byte memory ?

A 8 B 12

C 24 D 32

23 Four memory chips of 16 x 4 size have their address bases connected together. The system

will be of size

A 64 x 64 B 16 x 16

C 32 x 16 D 256 x I

24 How many addresses are required for 25 x 40 video RAM

A 1020 B 1900

C 1000 D 2000

25 Which of the following statements is incorrect for a micro-processor system using I/O

mapped I/O?

A I/O address space is greater. B I/O and memory spaces are distinct.

C Memory space available is greater. D Not all data transfer instructions are available.

26 A DMA module is transferring characters to main memory using cycle-stealing (getting the

system bus from CPU to do DMA transfer). The device is transmitting at 1 Mbps over a Local

Area Network. The CPU fetches instructions at the rate of 1 MIPS (one million instructions

per second). Assuming each memory location accessible in one bus cycle can hold 16 bits,

the CPU instruction fetch speed will degrade down to

A .9500 MIPS B .9250 MIPS

C .9375 MIPS D .9345 MIPS

27 In the disk storage aspect of data bases and application programs,

A unblocked record files and locate mode I/O are

faster

B blocked record files and locate mode I/O are

faster

C unblocked record files and move mode I/O are

faster

D blocked record files and move mode I/O are

faster

28 On receiving an interrupt from an I/O device, the CPU

A halts for a predetermined time B branches off to the interrupt service routine after

completion of the current instruction

C branches off to the interrupt service

routine immediately

D hands over control of address bus and data bus to the

interrupting device

29 Suppose it takes 100ns to across page table and 20 ns to access associative memory. If the

average access time is 28 ns, the corresponding hit rate is:

A 100 percent B 90 percent

C 80 percent D 70 percent

30 In which addressing mode, the effective address ofthe operand is generated by adding a

constant value to the contents of registere?

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A Absolute mode B Immediate mode

C Indirect mode D Index mode

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UGC NET Computer Science Test