Spi f28x

Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.

Digital Signal Controller TMS320F2812

Chapter 7 : Serial Peripheral Interface C28x


SPI Data Flow

SPI Shift RegisterSPI Shift Register SPI Shift RegisterSPI Shift Register

SPI Device #1 - Master SPI Device #2 - Slave

• Simultaneous transmits and receive

• SPI Master provides the clock signal

shift shift

clock


SPI Block Diagram

SPIRXBUF.15-0

SPIDAT.15-0

SPICLK

SPISOMI

SPISIMO

LSPCLK baudrate

clockpolarity

clockphase

C28x - SPI Master Mode Shown

SPITXBUF.15-0

LSBMSB

TX FIFO_0

TX FIFO_15

RX FIFO_0

RX FIFO_15


SPI Data Character Justification• Programmable data length of 1 to

16 bits

• Transmitted data of less than 16 bits must be left justified– MSB transmitted first

• Received data of less than 16 bits are right justified

• User software must mask-off unused MSB’s

11001001XXXXXXXX11001001XXXXXXXX

XXXXXXXX11001001XXXXXXXX11001001

SPIDAT - Processor #1

SPIDAT - Processor #2


SPI-A RegistersAddress Register Name

0x007040 SPICCR SPI-A configuration control register0x007041 SPICTL SPI-A operation control register0x007042 SPISTS SPI-A status register0x007044 SPIBRR SPI-A baud rate register0x007046 SPIEMU SPI-A emulation buffer register0x007047 SPIRXBUF SPI-A serial receive buffer register0x007048 SPITXBUF SPI-A serial transmit buffer register0x007049 SPIDAT SPI-A serial data register0x00704A SPIFFTX SPI-A FIFO transmit register0x00704B SPIFFRX SPI-A FIFO receive register0x00704C SPIFFCT SPI-A FIFO control register0x00704F SPIPRI SPI-A priority control register


SPI-A Configuration Control RegisterSPICCR @ 0x007040

0127 6 5-4

reserved

SPI CHAR.3-0

character length = number + 1

e.g. 0000b length = 11111b length = 16

SPI SW RESET 0 = SPI flags reset 1 = normal operation

CLOCK POLARITY0 = rising edge data transfer1 = falling edge data transfer

reserved

15-8 3


SPI-A Operation Control RegisterSPICTL @ 0x007041

01215-5 4 3

reserved

CLOCK PHASE0 = no CLK delay1 = CLK delayed 1/2 cycle

OVERRUN INT ENABLE0 = disabled1 = enabled

MASTER/SLAVE0 = slave1 = master

TALK0 = transmission disabled,

output pin hi-Z’d1 = transmission enabled

SPI INT ENABLE0 = disabled1 = enabled


SPI-A Baud Rate RegisterSPIBRR @ 0x007044

15-7 6-0

reserved SPI BIT RATE

SPICLK signal =

LSPCLK

(SPIBRR + 1)

LSPCLK

4

, SPIBRR = 3 to 127

, SPIBRR = 0, 1, or 2

Need to set this only when in master mode!


SPI-A Status RegisterSPISTS @ 0x007042

7 6 4-0

SPI INT FLAG (read only)• Set to 1 when transfer completed• Interrupt requested if SPI INT ENA

bit set (SPICTL.0)• Cleared by reading SPIBRXUF

RECEIVER OVERRUN (read/clear only)• Set to 1 if next reception completes before SPIRXBUF read• Interrupt requested if OVERRUN INT ENA bit set (SPICTL.4)• Cleared by writing a 1

reservedreserved

15-8

TX BUF FULL (read only)• Set to 1 when char written to SPITXBUF• Cleared when char in SPIDAT

5


SPI-A FIFO Transmit RegisterSPIFFTX @ 0x00704A

0

TXFFIL2

SPIFFEN TXFFST0TXFFST3

TXFFIEN

1234567

89101112131415

TXFFIL0TXFFIL1TXFFIL4 TXFFIL3

TXFFST1

TXFFINTCLR

TXFFST2

TXFFINT

TXFFST4TXFIFORESET

reserved

TX FIFO Status (read-only)00000 TX FIFO empty00001 TX FIFO has 1 word00010 TX FIFO has 2 words00011 TX FIFO has 3 words

10000 TX FIFO has 16 words

... ... ...

TX FIFO Interrupt LevelInterrupt when TXFFST4-0and TXFFIL4-0 match

SPI FIFOEnhancements

0 = disable1 = enable

TX FIFO Reset0 = reset (pointer to 0)1 = enable operation

TX FIFOInterrupt

(on match)Enable


TX FIFOInterrupt

Flag (read-only)0 = not occurred1 = occurred

TX FIFOInterruptFlag Clear0 = no effect1 = clear


SPI-A FIFO Receive RegisterSPIFFRX @ 0x00704B

0

RXFFIL2

RXFF-OVF CLR

RXFFST0RXFFST3

RXFFIEN

1234567

89101112131415

RXFFIL0RXFFIL1RXFFIL4 RXFFIL3

RXFFST1

RXFFINTCLR

RXFFST2

RXFFINT

RXFFST4RXFIFORESET

RXFF-OVF

RX FIFO Status (read-only)00000 RX FIFO empty00001 RX FIFO has 1 word00010 RX FIFO has 2 words00011 RX FIFO has 3 words

10000 RX FIFO has 16 words

... ... ...

RX FIFO Interrupt LevelInterrupt when RXFFST4-0and RXFFIL4-0 match

RX FIFO Reset0 = reset (pointer to 0)1 = enable operation

RX FIFOInterrupt

(on match)Enable


RX FIFOInterrupt

Flag (read-only)0 = not occurred1 = occurred

RX FIFOInterruptFlag Clear0 = no effect1 = clear

RX FIFOOverflow

Flag (read-only)0 = no overflow1 = overflow

RX FIFOOverflowFlag Clear0 = no effect1 = clear


SPI Summary

• Provides synchronous serial communications– Two wire transmit or receive (half duplex)– Three wire transmit and receive (full duplex)

• Software configurable as master or slave– C28x provides clock signal in master mode

• Data length programmable from 1-16 bits

• 125 different programmable baud rates


SPI Example 1: DAC TLV 5617

• Texas Instruments Digital to Analogue Converter (DAC) TLV 5617A– 10 MBPS SPI Data Communication – Dual Channel Analogue Output ( Out A + B) – 10 Bit resolution– /CS is connected to C28x GPIO – D0 at the Zwickau Adapter Board– REF – Voltage defines Analogue Range / 2 – SOIC-8– Operating Voltage : 0 to 3.3V


SPI Example : DAC TLV 5617• Timing Diagram:

© Texas Instruments SLAS234F – JULY 1999 – REVISED JULY 2002 ; page 6


SPI Example : DAC TLV 5617• Serial Data Format:

0

DATA0

SPD DATA6DATA9

DATA3

1234567

89101112131415

00DATA2 DATA1

DATA7

DATA4

DATA8

DATA5

R0PWRR1

SPDSpeed Control

0 = slow mode1 = fast mode

PWRPower Control

0 = normal operation1 = power down

R1 , R0 Register Select00: Write to DACB and Buffer01: Write to Buffer10: Write to DACA and update

DACB with Buffer 11: reserved


Lab 7: DAC TLV 5617• Objective:

– Generate a rising saw-tooth (0V…3.3V) at channel OUTA and a falling saw-tooth (3.3V…0V) at channel OUTB

– GPIO – D0 is DAC’s chip select (/CS) at the Zwickau Adapter Board– To measure the DAC outputs:

• Use JP7 for OUTA • Use JP8 for OUTB ( Zwickau Adapter Board)

– REF = 3.3V– Feedback the voltages into the C28x ADC:

• JP7 closed: OUTA ADCINA1• JP8 closed: OUTB ADCINB1


SPI Example 2: EEPROM M95080• ST Microelectronics EEPROM M95080

– 10 MBPS SPI Data Communication – Capacity: 1024 x 8 Bit – /CS is connected to C28x GPIO – D5 (Zwickau Adapter Board)– 6 Instructions:

• Write Enable, Write Disable• Read Status Register, Write Status Register• Read Data, Write Data

– SOIC-8– Single Power Supply : 3.3V


SPI Example : EEPROM M95080• Timing Diagram:

© ST Microelectronics Datasheet M95080 – November 2002, page 4


SPI Example : EEPROM M95080

00 = no protection

01 = 0x300 – 0x3FF protected



Status Register Write Protect 1 = no write access to SR 0 = normal operation

Write in progress

0 = no write cycle1 = write in progress

M95080 Status Register:M95080 Status Register:

0127 6 5 34

Write Enable Latch0 = write disabled1 = write enabled

WIPWELBP0SRWD 0 0 BP10

Block protect select



M95080 Instruction SetsM95080 Instruction Sets

InstructionInstruction DescriptionDescription CodeCode

WRENWREN Write EnableWrite Enable 0000 01100000 0110

WRDIWRDI Write DisableWrite Disable 0000 01000000 0100

EE Read Status Read Status RegisterRegister 0000 01010000 0101

WDSRWDSR Write Status Write Status RegisterRegister 0000 00010000 0001

READREAD Read DataRead Data 0000 00110000 0011

WRITEWRITE Write DataWrite Data 0000 00100000 0010


SPI Example : EEPROM M95080 • Timing Diagram WREN:

© ST Microelectronics ; Datasheet (8028.pdf) – November 2002; Page 8



• Timing Diagram RDSR:



SPI Example : EEPROM M95080 • Timing Diagram READ:



SPI Example : EEPROM M95080 • Timing Diagram WRITE:



Lab 7B: EEPROM M95080• Objective:

– Based on hardware of Zwickau Adapter Board– Store the value of 8 input switches (GPIO – B15…B8) into EEPROM –

Address 0x40 when command input button GPIO-D1 is pressed (low active).

– Read EEPROM-Address 0x40 and show its content on 8 LED’s ( GPIO-B7…B0) when command input button GPIO-D6 is pressed (low active).

– GPIO – D5 is EEPROM’s chip select (/CS) at the Zwickau Adapter Board

Education

Spi f28x