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Design and Fabrication of CMOS ISFET for pH Measurement

MSc viva voce presentation by: Chin Seng Fatt

Supervised by:1. Prof. Dr. Uda bin Hashim2. En. Mohd Khairuddin bin Md Arshad

School of Microelectronic EngineeringUniversiti Malaysia Perlis

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Presentation Outline

IntroductionTCAD SimulationMask DesignDevice FabricationDevice PackagingDevice CharacterizationConclusionAcknowledgments

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What is pH?

The pH relation originated from Danish Chemist Sorenson in1909.

pH is the unit of measurement for determining the acidity of alkalinity of a solution.

The math definition of pH is the negative logarithm of the molar H+:

pH = - log ([H+])

Source: wwww.emersonprocess.com

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Importance of pH Measurement

Control a Chemical ReactionMost inorganic reactions are pH neutralizations

The rate of many reactions depend on the availability of H+ or OH- ions.

Bacterial growth is pH dependent.

Corrosion Control

Water and Wastewater Treatment

Raw Material and Product Quality Control

Source: wwww.emersonprocess.com

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pH Measurement Methods

Litmus paperSimpleQuick measurementColor indication

Glass pH ElectrodeHigher accuracyBetter selectivity

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This research proposed an ISFET that can measures the ionic activity in a electrolyte solution and can be fabricated using CMOS technology and materials without extra processing stepsThe advantages of this proposed ISFET include:

Fast and direct in-situ monitoringRobust and sturdierSmall size

This research proposed an ISFET that can measures the ionic activity in a electrolyte solution and can be fabricated using CMOS technology and materials without extra processing stepsThe advantages of this proposed ISFET include:

Fast and direct in-situ monitoringRobust and sturdierSmall size

Litmus paperColor indication2 pH value limitationPreliminary measurement

Glass pH electrodeBulky, fragileHigh cost of Initial setupRoutine maintenance

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What is ISFET?

ISFET is Ion Sensitive Field Effect Transistor

Known as chemical or ion sensor

Sensing method based on potentiometric detection

First developed by Prof. Bergveld in 1970 by using SiO2 as sensing layer

Advantages: small size, robust, fast response

Applications: medical, agriculture, food industry, environment monitoring

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MOSFET and ISFET

Basically the structure of the ISFET is similar to MOSFET

The physical difference in the ISFET is the replacement of the gate electrode of the MOSFET by the series combination of reference electrode, electrolyte and ion sensing layer

MOSFET operation was controlled by the gate electrode while ISFET operation was controlled by ion concentration in the electrolyte

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Flowchart of How ISFET works

ISFETISFETGate

voltage exceeds threshold

Gate voltage exceeds threshold

Inversion layer

formed atSiO2/Si

Inversion layer

formed atSiO2/Si

N+ source supply

electrons

N+ source supply

electrons

N+ drain make

electrons flow

N+ drain make

electrons flow

Positive voltage

applied to n+ drain

Positive voltage

applied to n+ drain

Electrons flow from S

to D

Electrons flow from S

to D

Gate voltage controls

electrons and Id

Gate voltage controls

electrons and Id

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Objective of Research

To characterize the ISFETTo design the ISFET

To fabricate the ISFET

Research Goals

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Scope of Research

Reviewing and understanding the principles of ISFET

Design and simulate the ISFET with TCAD

Design and fabricate the ISFET masks

Fabrication of the ISFET

Testing of the ISFET

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Synopsys TCAD is used to perform process and device simulation on ISFET.

Process simulation models the fabrication steps of the ISFET.

Simulation starts with definition of structure and finishes with a complete device

The process simulator used is TSUPREM4

Virtual ISFET simulated byTSUPREM4

TCAD Process Simulation

N N

Si3N4 / SiO2 gate

Source metalcontact

Drain metalcontact

Gate metalcontact

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TCAD Device Simulation

I-V simulation by Medici

Device simulation in TCAD is the simulation of the device electrical characteristics.

The TUSPREM4 ISFET is simulated for its gate and drain characteristics.

The characteristics of the ISFET are simulated by applying a set of voltage biases and sweep the biases from one point to another.

Device simulator used is Medici.

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Mask Design

Layout of ISFET similar to MOSFET: gate, source, drain, contacts.

The extended source drain regions separates the metal contacts from gate region during immersion and for straightforward encapsulation.

Mask making process is straightforward: CAD design and mask printing.

CAD design of individual dies replicated on a wafer to create the wafer layout and then transferred to actual mask.

A total of 6 masks created. Material used as the actual mask is transparency.

Schematic design of the ISFET

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Well Mask

(b)

(c)

(a)

(a) Schematic design of well(b) AutoCAD design of the Well mask(c) Photograph of the actual mask

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Source Drain Mask

(a)

(b)

(c)

(a) Schematic design of source drain(b) AutoCAD design of the source drain masks(c) Photograph of the actual source drain masks

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Gate Mask

(b)

(c)(a)

(a) Schematic design of Gate (b) AutoCAD design of the Gate mask(b) Photograph of the actual Gate mask

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Contact Mask

(b)

(c)

(a) Schematic design of Contact (b) AutoCAD design of Contact mask(b) Photograph of actual Contact mask

(a)

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Metal Mask

(b)

(c)

(a)

(a) Schematic design of metal contact(b) AutoCAD design of the Metal mask(c) Photograph of the actual Metal mask

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Fabrication of ISFET

ISFET is fabricated using CMOS technology without any post

processing steps.

All fabrication steps are performed in-house in Microfabrication Lab.

The starting material is a 4 inch p-type Silicon wafer.

The gate material of the ISFET is made of SiO2 and Si3N4, both

CMOS compatible materials.

Six masking steps: creation of n-well, n and p source drains, gate,

contact and metal.

The etching of Si3N4 and SiO2 is done using buffered oxide etch

(BOE) solution.

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Equipment modulesPECVD systemPVD systemWet/dry oxidation furnaceN/P diffusion furnaceMask aligner/exposure systemWet etch moduleWafer spinner Hot plate

ConsumablesSilicon wafer 4 inchBuffered oxide etch (BOE)Acetone Positive photoresistDI waterAluminum foilAluminum etchantSiH4 gasPurified oxygen gasPurified nitrogen gas

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Process Flow of ISFET Fabrication

1. Starting materialSi, p-type, <100>

1. Starting materialSi, p-type, <100>

2. Field oxidationWet oxidation, 1000°C95 min 5598 ÅWet oxidation furnace

2. Field oxidationWet oxidation, 1000°C95 min 5598 ÅWet oxidation furnace

3. Well creationWell Mask, positive photoresistResist development: 30sOxide etch: 30 min

3. Well creationWell Mask, positive photoresistResist development: 30sOxide etch: 30 min

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Process Flow of ISFET Fabrication

4. Well phosphorus diffusionSpin-on dopant phosphorusDiffusion drive-in: 6 hoursN-diffusion furnace

4. Well phosphorus diffusionSpin-on dopant phosphorusDiffusion drive-in: 6 hoursN-diffusion furnace

6. Boron source drain formationSource Drain Mask, positive photoresistSpin on dopant - boronP-Diffusion furnace: 900°C, 30 min

6. Boron source drain formationSource Drain Mask, positive photoresistSpin on dopant - boronP-Diffusion furnace: 900°C, 30 min

5. Phosphorus source drain formationSource Drain Mask, Positive photoresistSpin on dopant - phosphorusN-Diffusion furnace: 850°C, 25 min

5. Phosphorus source drain formationSource Drain Mask, Positive photoresistSpin on dopant - phosphorusN-Diffusion furnace: 850°C, 25 min

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Process Flow of ISFET Fabrication7. Gate oxide formationGate Mask photolithographyGate oxidationDry oxidation furnace1000°C 60 min 556 Å

7. Gate oxide formationGate Mask photolithographyGate oxidationDry oxidation furnace1000°C 60 min 556 Å

8. Silicon nitride PECVD deposition Deposition rate: 24.34nm/minDeposited thickness: 486.7 Å

8. Silicon nitride PECVD deposition Deposition rate: 24.34nm/minDeposited thickness: 486.7 Å

9. Contact BOE etch formationOxide & nitride etch with BOEEtch time:30 min

9. Contact BOE etch formationOxide & nitride etch with BOEEtch time:30 min

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Process Flow of ISFET Fabrication10. PVD contact metallizationPVD moduleAluminum thickness: 1541 ÅAnnealing 450 °C, 45 min, N2 gas Metal Mask, positive photoresistEtch rate Al: 308.2 Å/minEtch time: 5 min approx.

10. PVD contact metallizationPVD moduleAluminum thickness: 1541 ÅAnnealing 450 °C, 45 min, N2 gas Metal Mask, positive photoresistEtch rate Al: 308.2 Å/minEtch time: 5 min approx.

Photography ofthe completed ISFET wafer

Photography ofthe completed ISFET wafer

ISFET die with metal gate for functionality evaluation

ISFET die with metal gate for functionality evaluation

ISFET die with Si3N4gate will be packaged and tested in pH solutions

ISFET die with Si3N4gate will be packaged and tested in pH solutions

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Packaging of ISFET

The packaging process of ISFET: wafer dicing, die mounting, wire bonding and encapsulation.

The ISFET die is separated from the wafer and mounted on a PCB as a platform and contacts are wired from die to the PCB.

Since the ISFET will work in electrolyte solution, an epoxy is used to encapsulate the edge of the ISFET die, the wire bonding and the PCB.

The sensing gate is the only area which is exposed to the solution will not be covered.

The type of epoxy used is silicone rubber.

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1. Diced ISFET from wafer1. Diced ISFET from wafer

4. ISFET encapsulation4. ISFET encapsulation

2. Mounting ISFET on PCB3. Wire bonding

2. Mounting ISFET on PCB3. Wire bonding

Packaging Flow of ISFET

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Characterization of ISFET

The operation of ISFET is analyzed from IdVd and IdVg curves.

IdVd and IdVg measurements are done using Keithley 4200 Semiconductor Parameter Analyzer.

Two tests are performed on ISFET: functionality test at wafer level and pH test.

In functionality test, the ISFET with metal gate is under probesconnected to the analyzer.

In pH test, the ISFET is immersed in acidic, neutral and base solutions (pH 4, pH 7, pH 10). All solutions obtained from Orion.

All measurements were done using Ag/AgCl reference electrode from Hanna Instruments.

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Functionality Test Setup

Schematic setupSchematic setup

(a)

(b) (a) Dark shielded box– wafer probe

station (b) Keithley 4200 Semiconductor

Parameter Analyzer

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pH Test Setup

(a) Keithley 4200 Semiconductor Parameter Analyzer(b) ISFET(c) Reference Electrode(d) pH buffer solutions

(a)

(b) (c)

(d)

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Output characteristics of ISFET

I-V measurements of ISFET performed using Keithley 4200 SPA through wafer probe stationI-V measurements of ISFET performed using Keithley 4200 SPA through wafer probe station

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IdVd curves at Vg=5.0V for n-ISFET when measured in three levels of pH buffer solution

IdVd curves at Vg=5.0V for n-ISFET when measured in three levels of pH buffer solution

Sensitivity, S = Δ Vth / Δ pH = Δ Vg / Δ pH = 40.34 mV/pH

Sensitivity, S = Δ Vth / Δ pH = Δ Vg / Δ pH = 40.34 mV/pH

pH Response of n-ISFET

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IdVd curves at Vg=-5.0V for p-ISFET when measured in three levels of pH buffer solution

IdVd curves at Vg=-5.0V for p-ISFET when measured in three levels of pH buffer solution

Sensitivity, S = Δ Vth / Δ pH = Δ Vg / Δ pH= 34.83 mV/pH

Sensitivity, S = Δ Vth / Δ pH = Δ Vg / Δ pH= 34.83 mV/pH

pH Response of p-ISFET

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DiscussionsISFET operates by accumulating H+ from solution at gate.

The positive charge on gate is mirrored on the inner side of semiconductor where a channel of negative charge occurs. This makes ISFET conductive.

The lower pH, more H+ accumulates, more current flow between source and drain.

Image Source: http://www.my.endress.com/

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ConclusionsA CMOS ISFET pH sensor has been successfully designed, fabricated and characterized.

Simulation on ISFET is successfully achieved using TCAD.

Mask layout successfully designed using AutoCAD and fabricated on transparency masks.

Fabrication of ISFET using all in-house CMOS technology required no extra masking or post processing step.

The ISFET successfully detected buffer solutions of different pH.

Based on the results obtained, the CMOS ISFET showed a fairly good response as a pH sensor and has potential for commercialization.

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Research Achievements

2

3

1

Bronze Medal

Silver Medal

Gold Medal

5Local Conference

3Regional Conference

4International Conference

1International Journal

Research Publications Award Medals

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Recommendation

SPICE simulation

Simulation of pH response of ISFET

Miniaturization of ISFET

Sub-micron size device, chrome masks

Lower cost of fabrication, mass production

Packaging of the ISFET

Precise wafer dicing by automation

Proper encapsulation material and technique

Sampling Experiments

Larger samples of pH on both acidic and basic tests

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Acknowledgement

The financial support from UniMAP and Malaysian Ministry of Science, Technology and Innovation (MOSTI).

Guidance and advices from supervisors

Motivational supports from families, researchers, friends.