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Microprocessor-Based Systems
Dr. Randa Elanwar
Lecture 2
Lecture Content
• Microprocessor ALSU functions
– Arithmetic operations
– Logical operations
– Shift operations
– Complete instruction set
• Microprocessor 8 bits bus architecture
• Microprocessor 8/16 bits bus architecture
2Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Addition)
x7x6x5x4 x3x2x1x0
+
y7y6y5y4 y3y2y1y0
3Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7 x7
c7 z7
Full Adder1
y1 x1
c1 z1
Full Adder0
y0 x0
c0 z0
………MUX
k1
cin
CF
D Q
CLK
CFout
GND
K1 instruction Meaning0 ADD X, Y Z = X plus Y1 ADC X, Y Z = X plus Y plus CFout
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Addition)
• If we want to increment x:
• Let Y = 1 or (Y=0 and Cin = 1)
4Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CF
D Q
CLK
CFout
GND
MUX
k1
1
k3
K3 K1 instruction Meaning1 0 ADD X, Y Z = X plus Y1 1 ADC X, Y Z = X plus Y plus CFout
0 1 Inc X Z = X plus 1
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Subtraction)
• X minus Y = X plus 2’s complement of Y
• The carry is complemented and becomes a borrow bit
5Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CF
D Q
CLK
CFout
GND
MUX
k1
1
k3
k2
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Subtraction)
• 2’s complement of Y = (1’s complement of Y) + 1
• 1’s complement can be implemented by XOR gate: (Y xor 0 = Y), (Y xor 1 = Y’)
6Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CF
D Q
CLK
CFout
GND
MUX
k1
1
k3
k2
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Subtraction)
• 2’s complement of Y = (1’s complement of Y) + 1
• ‘1’ comes from the XOR gate at Cin
7Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CF
D Q
CLK
CFout
GND
MUX
k1
1
k3
k2
Microprocessor bus architecture and instruction sets
• Arithmetic Logic Shift Unit (Subtraction)
• The carry is complemented and becomes a borrow bit at XOR gate before the carry flag and stored in it
8Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CF
D Q
CLK
CFout
GND
MUX
k1
1
k3
k2
Microprocessor bus architecture and instruction sets
Arithmetic Logic Shift Unit
• If k2 = 0 (addition) CF stores carry
• If k2 = 1 (subtraction) CF stores borrow
9Microprocessor-Based Systems Dr. Randa Elanwar
Full Adder7
y7
x7
c7 z7
Full Adder1
y1
x1
c1 z1
Full Adder0
y0
x0
c0 z0
………MUX
k3
cin
CFD Q
CLKCFout
GND
MUX
k1
1
k3
k2
K2K3 K1 instruction Meaning1 1 0 ADD X, Y Z = X + Y1 1 1 ADC X, Y Z = X + Y + CFout
1 1 0 SUB X, Y Z = X - Y1 1 1 SBB X, Y Z = X - Y - BRW0 0 1 Inc X Z = X + 11 0 1 DEC X Z = X - 1
Microprocessor bus architecture and instruction sets
10Microprocessor-Based Systems Dr. Randa Elanwar
ALSU
Xin
Yin
Z
mode
•k1, k2 and k3 are the mode selection lines for arithmetic operations
•There are more mode selection lines for logical and shift operations
4x1 MUX 4x1 MUX
z7 z0
K4
K5
Shift Block
K1
K2K3……..
Logical Block
K1
K2
……..
Arithmetic Block
K1
K2K3…….. z’0z’’0z’’’0z’’’7 z’’7 z’7
x0x7y0y7
K5 K4 Operation0 0 Logic0 1 Arithmetic1 0 Shift1 1 Not used
…….
Microprocessor bus architecture and instruction sets
• Logical operations:
• If we want to AND X, Y
11Microprocessor-Based Systems Dr. Randa Elanwar
X 0101 0110 K1 K2 OperationY 1011 0101 0 0 ANDX.Y 0001 0100 1 0 XOR
0 1 OR1 1 NOT
x7 x0 x7 x0 x7 x0 x7 x0y7 y0y7 y0y7 y0
4x1 MUX 4x1 MUX
z7 z0
K1
K2
…….
…….
……. ……. …….
……. ……. …….
…….
Microprocessor bus architecture and instruction sets
• Shift operations:
• To shift in both directions
12Microprocessor-Based Systems Dr. Randa Elanwar
D Q D Q D QRser in
… …
D Q D Q D Q
Rser in
MUXMUXMUX
The flip flop stores a certain value, with each clock 1 bit is shifted to the right and new data is stored
Microprocessor bus architecture and instruction sets
• The ALSU shift unit:
• Shift can be used to perform arithmetic operations
• SAL: Shift Arithmetic Left (*) SAR: Shift Arithmetic Right (/)
0010 2 1000 8
0100 4 0100 4
1000 8 0010 2
13Microprocessor-Based Systems Dr. Randa Elanwar
……….
RSser inLSser in
x0x1x2x3x4x5x6x7
z0z1z2z7
K1
K1 Operation0 Shift left1 Shift Right
Microprocessor bus architecture and instruction sets
14Microprocessor-Based Systems Dr. Randa Elanwar
ROR: ROtate Right
The register restores the original content after 8 clocks
RCR: Rotate through Carry Right
The register restores the original content after 9 clocks
CF
CF
Microprocessor bus architecture and instruction sets
• Full Instruction set
• K3 K2 K1 instruction Operation
• 0 0 0 SHL Shift X by 1 bit left (LSin=0)
• 0 0 1 SHR Shift X by 1 bit right (RSin=0)
• 0 1 0 SAL Shift arithmetic X by 1 position left (LSin=0)
• 0 1 1 SAR Shift arithmetic X by 1 position right (Rsin=x7)
• 1 0 0 ROL Rotate left X by 1 position (LSin=x7)
• 1 0 1 ROR Rotate right X by 1 position (LSin=x0)
• 1 1 0 RCL Rotate through carry left
• 1 1 1 RCR Rotate through carry right
15Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• Full Instruction set• K5 K4 K2 K3 K1 instruction Meaning
• 0 1 0 1 0 ADD X, Y Z = X + Y
• 0 1 0 1 1 ADC X, Y Z = X + Y + Carry
• 0 1 1 1 0 SUB X, Y Z = X - Y
• 0 1 1 1 1 SBB X, Y Z = X - Y - Borrow
• 0 1 0 0 1 Inc X Z = X + 1
• 0 1 1 0 1 DEC X Z = X – 1
• 0 0 0 x 0 AND X, Y Z = X . Y
• 0 0 1 x 0 XOR X, Y Z = X Y
16Microprocessor-Based Systems Dr. Randa Elanwar
+
Microprocessor bus architecture and instruction sets
• All the previous discussion was describing an ALSU manipulating 8 bit (byte) data type.
• If we want to construct an ALSU manipulating 16 bit (word) data type, the number of flip flops and gates has to be doubled.
• If we want to construct an ALSU manipulating both 8 bit and 16 bit data, each ‘carry’ or ‘Most Significant Bit (MSB)’ has to be passed through a multiplexer to select between (C7 and C15) or (x7 and x15) with mode selection line k6.
17Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• 8 bit bus architecture
18Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
Reg A
Reg B
Reg C
Reg D
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k5…k1
Reg E
Reg H
Reg L
All registers: A, B, C, D, E, H, L, T1 and T2 are 8 bit registers
The bus is composed of 8 signaling lines
Microprocessor bus architecture and instruction sets
• 8 bit bus architecture
19Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
Reg A
Reg B
Reg C
Reg D
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k5…k1
Reg E
Reg H
Reg L
ALSU is composed of 8 bit Arithmetic, logic, shift units
ALSU has five mode selection lines k1 k5
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture
20Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
AH
BH
CH
DH
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k6…k0
SI
DI
AL
BL
CL
DL
All registers: AX, BX, CX, DX, SI, DI, T1 and T2 are 16 bit registers
The bus is composed of 16 signaling lines
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture
21Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
AH
BH
CH
DH
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k6…k0
SI
DI
AL
BL
CL
DL
All registers: e.g., AX is composed of 2 parts AHand AL to hold the Higher 8 bits and the Lower 8 bits. Each has its own CScontrol signal
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture
22Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
AH
BH
CH
DH
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k6…k0
SI
DI
AL
BL
CL
DL
AL, BL, CL, DLare connected to the lower bus lines while AH, BH, CH, DH are connected to the higherbus lines
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture
23Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
AH
BH
CH
DH
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k6…k0
SI
DI
AL
BL
CL
DL
ALSU has 16 bit units (H, L)
ALSU has six mode selection lines k1 k6
k6 allows working on either 8 or 16 bit data type
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture
24Microprocessor-Based Systems Dr. Randa Elanwar
T2
CLKT2
AH
BH
CH
DH
CLKT1
T1
CF
CSALU
Xin
Yin
Z
ALSU
k6…k0
SI
DI
AL
BL
CL
DL
SI: source index register, 16 bits register, it has only one CScontrol.
DI: destination index register, 16 bits register, it has only one CScontrol.
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture: Instructions
• MOV BX, AX
– This instruction copies the content of AL to BL and AH to BH
– CS of AX (both AL, AH) is low, then
– CLK of BX (both BL, BH) is low
• MOV BL, AL
– This instruction copies the content of AL to BL only
– CS of AL only is low, then
– CLK of BL only is low
25Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture: Instructions
• MOV BH, AH
– This instruction copies the content of AH to BH only
– CS of AH only is low, then
– CLK of BH only is low
• MOV AH, AL
– Not possible
26Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture: Instructions
• MOV SI, AX
– This instruction copies the content of AX to SI
– CS of AX (both AL, AH) is low, then
– CLK of SI is low
• MOV SI, BL
– Not possible
– BL has 8 bits and SI is a one part 16 bit register
27Microprocessor-Based Systems Dr. Randa Elanwar
Microprocessor bus architecture and instruction sets
• 8/16 bit bus architecture: Instructions
• MOV BX, DI
– This instruction copies the content of DI to BX
– CS of DI is low, then
– CLK of BX (both BL, BH) is low
• MOV SI, DI
– This instruction copies the content of DI to SI
– CS of DI is low, then
– CLK of SI is low
28Microprocessor-Based Systems Dr. Randa Elanwar