Microprocessors-based systems (under graduate course) Lecture 1 of 9

Microprocessor-Based Systems

Dr. Randa Elanwar

Lecture 1

Lecture Content

• Introduction to microprocessors,

• Comparison of typical microprocessors

• The 8086 microprocessor architecture:

– The microprocessor system: CPU, memory, I/O

– The microprocessor Pin outs, clock circuitry,

– Bus structure: address bus, data bus, and control bus connections

– The microprocessor instruction sets

2Microprocessor-Based Systems Dr. Randa Elanwar

Introduction to microprocessors

• Definition: Microprocessor

• Is a digital integrated circuit(s) capable of executing program

• Definition: Program

• Is a set of instructions to be executed in sequence

• Definition: Central processing unit (CPU)

• Is a logic circuit controlling the operation of the computer

• Microprocessors perform the function of a CPU in micro-computer systems.



• Microprocessors started at mid 70’s

• The data/information processed by a microprocessor (electronic circuits) is usually represented in binary format.

• Each binary digit represent a power of 2. A binary digit is often called a ‘bit’

• The binary system uses only two symbols zero (0) and one (1)

• Binary numbers are often called ‘binary words’.

• A 4-bit binary word is called a ‘nibble’.

• An 8-bit binary word is called a ‘byte’.

• A 16-bit binary word is called a ‘word’.

• A 32-bit binary word is called a ‘long word’/‘double word’.



• Binary information is fed to the electronic circuits by voltage levels.

• Standard logic circuits use 5 volts power supply.

• Low voltage circuits use 3 volts power supply, thus consumes less power as in portable computers.


•Binary information is =1 if 3v <= voltage <= 5v, and information is =0 if 0v <= voltage <= 1v

•If 1v < voltage < 3v, the binary information level is considered undefined. Low

High

Undefined

0 v

1 v

3 v

5 v


• The simple microprocessor major parts are: The central processing unit (CPU), memory, and the input/output circuitry.

• Connecting these three parts are three sets of parallel lines called buses. The three buses are the address bus, the data bus and the control bus.



The Central Processing Unit (CPU)

• The CPU controls the operation of the computer.

• The CPU fetches binary coded instructions from memory, decodes the instructions into simple actions and carries out these actions in sequence of steps.

• The CPU also contains an “address counter”, which holds the address of the next instruction or data item to be fetched from memory or temporary storage registers.



Memory

• Memory has 2 purposes: store the binary codes of instructions to be carried out and store the binary coded data with which the computer is going to be working.

• Memory types are either ROMs or RAMs. These are implemented using logical gates circuitry (e.g. D flip flops)


Clock

+ -

Clock (CLK)


• If the flip flop is +ve edge sensitive, the output (Q) will be equal to the input (D) only at the +ve edge of the clock (active high)

• If the flip flop is -ve edge sensitive, the output (Q) will be equal to the input (D) only at the -ve edge of the clock (active low)



• Example (active high)


Input

Output

CLK


• Inputs and Outputs (I/O)

• The I/O section allows the computer to take in data or send out data.

• Peripherals such as keyboards, monitors, printers and modems are connected to the I/O section through ports.

• The simplest type of input or output port is just a set of parallel D flip-flops (Register)

Example: 8 bit register



• Inputs and Outputs (I/O)

• In the 8 bit register we have 1 pin for GND, 8 pins for inputs, 8 pins for outputs, 1 for clock and 2 for supply (20 pins)

• For an input port, the D inputs will be connected to the external device and the Q outputs will be connected to the data bus which runs to the CPU.

• For an output port, the D inputs will be connected to the data bus which runs to the CPU and the Q outputs will be connected to the external device.

• In either cases the data is transferred to/from the bus is enabled only when receiving a control signal from the CPU (usually the clock)



• Example:

• It is not a must that the data stored in register A is the same stored in register B because this depends on their clocks.

• In most cases a master clock only is available thus we need another control signal such that data goes to/from the intended registers only (chip selection CS)


Reg A Reg B

8 input lines

CLKA CLKB


• Example: to transfer data from Reg A to Reg B


Reg A Reg B

8 input lines

CLKA CLKB

CSA CSB

CSA

CLKB


• The address bus

• It consists of 16, 20, 24, 32 parallel signal lines. On these lines the CPU sends out the address of the memory location that is to be written to or read from.

• The number of memory locations that the CPU can address is determined by the bus size.

• If the CPU has N address lines it can address 2N memory locations.


# Address lines # Memory locations

16 65,536

20 1,048,576

24 16,777,216

Introduction to microprocessors• The data bus• It consists of 8, 16 or 32 parallel signal lines. They are

bidirectional lines. • The CPU can read data from memory/port and write data to

memory/port on these lines.• Many devices have their outputs connected to the data bus

thus they must have a selection signal.

• The control bus• It consists of 4 to 10 parallel signal lines.• The CPU sends out signals on the control bus to enable the

outputs of addressed memory or port devices.• Typical control bus signals are Memory Read, Memory Write,

I/O Read and I/O Write.


Introduction to microprocessors• Example: Memory Read• To read a byte of data from a memory location, the CPU sends out

the memory address of the desired byte on the address bus and then sends out a Memory Read signal on the control bus.

• The Memory Read signal enables the addressed memory device to output a data word onto the data bus.

• The data word from memory travels along the data bus to the CPU.

• Example: 3 Instructions program1. Input a value from a keyboard connected to the port at address

05H2. Add 7 to the value read in3. Output the result to a display connected to the port at address

02H




Comparison of typical microprocessors


8086 8088

16 bit microprocessor,16 bit data bus, 20 bit address bus

16 bit microprocessor, 8 bit data bus, 20 bit address bus

The arithmetic logic unit has internalregisters

Same as 8086

Instructions work with16 bit binary words

Same as 8086

Read/write data either8 or 16 bit at a time

Read/write data either 8 bits at a time

Can address 220

memory locationsCan address 220

memory locations

Reads 16 bit word in 1 operation

Reads 16 bit word in 2 operations

The 80186 is an improved version of 8086 and 80188 is an improved version of 8088 with instruction set that is a superset of the instruction set of the 8086. Both are 16 bit microprocessors.

The 80286 is a 16 bit microprocessor advanced version of the 8086 designed for multitasking microcomputers.

The 80386 is a 32 bit microprocessor which can address up to 4 gigabytes memory used in multitasking microcomputers.

Self study: you can read more about the competitive microprocessors and find out the aspects of comparison

Microprocessor bus architecture and instruction sets

• Before we talk about how to write a program for the 8086 we first have to discuss its internal features: ALU, flags, registers, instruction byte queue and segment registers.

• The 8086 CPU is divided into 2 independent functional parts:

1. Bus interface unit (BIU): sends out addresses, fetches instructions from memory, reads/writes data from/to ports and memory

2. Execution unit (EU): tells the BIU where to fetch the instructions and data from, decodes and execute instructions




To understand this architecture and function of each component we will have to discuss several simpler structures


• Example 1: Simple bus architecture


Reg A Reg BCLKA CLKB

CSA CSB

Reg C Reg DCLKC CLKD

CSC CSD

CLRD

Reg E

CLKE

CSE

CNT Up

CNT DN

•In this architecture we have 3 registers with CS signal (A, B and C)•Reg D has an active low CLR signal•Reg E has two active low signal (CNT UP) to increment its contents by 1 at every –ve edge and (CNT DN) to decrement its contents by 1 at every –veedge •We will discuss how this architecture executes these simple instructions:MOV B, A CLR A INC B



CSA

CLKB

MOV B, A: means move the content of A to BWe select Reg A to output data on busWe activate Reg B clock to read the data on bus

CLR A: Reg A doesn’t have a CLR signal inputUse Reg D to clear its content move this content to Reg A (MOV A, D)

CSD

CLKA

CLRD

PD

PD

CSB

CLKE

CSE

CLKB

CNT UP

INC B:Reg B doesn’t have a CNT UP signal inputmove this content to Reg E (MOV A, E)Use Reg E to increment its contentmove this content to Reg B (MOV B, E)

PD: propagation delay


• Example 2: Advanced bus architecture


Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

In this architecture: Reg A is known as “Accumulator”i.e. accumulate results of ALSU




Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

The buffer is used to isolate the output of Reg A if CSA is low and as a 8 bit buffer if CSA is high




Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

T1 is a temporary register. Takes the input only from the bus and outputs its content as ALSU Yin. Doesn’t have to be isolated, has no CS control line




Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

ALSU: Arithmetic Logic Shift Unit. It does binary/decimal arithmetic operations (+,-,*,/), logic operations (>,=,<,complement) and shift operations




Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

If we want to add A and B:ADD A, B

Means A+BAThe micro-operations will be:1. Move B to T12. Select ALSU addition Mode3. Set CSALSU low (result Z is on the

bus)4. Set CLKA low to move (A takes

the result)




Reg A

CLKA

CSA Reg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSDReg E

CLKE

CSE

CLKT

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

CF: Carry flag, a flip flop that holds the carry for arithmetic operations

To avoid racing (continuous addition, we introduce time delay between input A (Xin) and output A (Z) using a master-slave flip flop

To add Reg B and C for example we need a new architecture




T2

CLKT2

Reg A

CLKA

CSAReg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSD

CLKT1

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

Now if we want to add B and C and store the result in DThe micro-operations will be:1. Move B to T12. Move C to T23. Select ALSU addition Mode4. Set CSALSU low (result Z is on the

bus)5. Set CLKD low to move (D takes

the result)




T2

CLKT2

Reg A

CLKA

CSAReg B

CLKB

CSBReg C

CLKC

CSCReg D

CLKD

CSD

CLKT1

T1

CF

CSALU

Xin

Yin

Z

ALSU

mode

Thus structure enables the addition of 1 byte to 1 byte

Ex: 0011 1010+1011 11001111 0110

cc c

Multi-byte addition needs store the carry in a D flip flop Carry flag

Education

Microprocessors-based systems (under graduate course) Lecture 1 of 9