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TEMA
SOLUTIONS
VLSI TITLES
9941928222
8680802110
Any queries contact
9941928222/8680802110
29,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43556664
Mobile : +91-8680802110
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IEEE VLSI TITLES 2015-2016
S.No Titles Year
1. A Synergetic Use of Bloom Filters for Error Detection and
Correction. 2015
2. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based
on Multilevel Conditional Probability. 2015
3.
An Efficient Constant Multiplier Architecture Based on
Vertical-Horizontal Binary Common Sub-expression
Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
2015
4. Implementation of Subthreshold Adiabatic Logic for Ultralow-
Power Application. 2015
5. Single-Supply 3T Gain-Cell for Low-Voltage Low-Power
Applications. 2015
6. A Single-Ended With Dynamic Feedback Control 8T
Subthreshold SRAM Cell. 2015
7. Exploiting Same Tag Bits to Improve the Reliability of the
Cache Memories. 2015
8. Aging-Aware Reliable Multiplier Design With Adaptive Hold
Logic. 2015
9. Recursive Approach to the Design of a Parallel Self-Timed
Adder. 2015
10. Fault Tolerant Parallel Filters Based on Error Correction Codes. 2015
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9941928222/8680802110
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Chennai-17. Ph : 044-43556664
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11. Synthesis of majority and minority logic networks. 2015
12. Coplanar Full Adder in Quantum-Dot Cellular Automata via
Clock-Zone Based Crossover. 2015
13. Fast and Wide Range Voltage Conversion in Multisupply
Voltage Designs. 2015
14. Energy and Area Efficient Three-Input XOR/XNORs With
Systematic Cell Design Methodology. 2015
15. Fault Tolerant Parallel FFTs Using Error Correction Codes and
Parseval Checks. 2015
16. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 −
1, 2n − 1, 2n}. 2015
17. In-Field Test for Permanent Faults in FIFO Buffers of NoC
Routers. 2015
18. Knowledge-Based Neural Network Model for FPGA Logical
Architecture Development. 2015
19. Level-Converting Retention Flip-Flop for Reducing Standby
Power in ZigBee SoCs. 2015
20. Reliable Low-Power Multiplier Design Using Fixed-Width
Replica Redundancy Block. 2015
21. A Novel Quantum-Dot Cellular Automata X-bit × 32-bit
SRAM. 2015
22. A Low-Latency and Low-Power Hybrid Scheme for On-Chip
Networks. 2015
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9941928222/8680802110
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Chennai-17. Ph : 044-43556664
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23. Partially Parallel Encoder Architecture for Long Polar Codes. 2015
24. An Efficient List Decoder Architecture for Polar Codes. 2015
25. Network-on-Chip for Turbo Decoders. 2015
26. A High-Throughput VLSI Architecture for Hard and Soft SC-
FDMA MIMO Detectors. 2015
27. Code Compression for Embedded Systems Using Separated
Dictionaries. 2015
28. Design for Testability of Sleep Convention Logic. 2015
29.
Design of an Ultra-low Voltage 9T SRAM With Equalized
Bitline Leakage and CAM-Assisted Energy Efficiency
Improvement.
2015
30. Efficient Coding Schemes for Fault-Tolerant Parallel Filters. 2015
31. Fully Reused VLSI Architecture of FM0/Manchester Encoding
Using SOLS Technique for DSRC Applications. 2015
32. High-Frequency CMOS Active Inductor: Design Methodology
and Noise Analysis. 2015
33. On the Nonvolatile Performance of Flip-Flop/SRAM Cells With
a Single MTJ. 2015
34. Quaternary Logic Lookup Table in Standard CMOS. 2015
35. Z-TCAM: An SRAM-based Architecture for TCAM. 2015
36. Design of Self-Timed Reconfigurable Controllers for Parallel
Synchronization via Wagging. 2015
37. Reverse Converter Design via Parallel-Prefix Adders: Novel 2015
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9941928222/8680802110
29,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43556664
Mobile : +91-8680802110
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Components, Methodology, and Implementations.
38. A Generalized Algorithm and Reconfigurable Architecture for
Efficient and Scalable Orthogonal Approximation of DCT. 2015
39. Aggressive Voltage Scaling Through Fast Correction of
Multiple Errors With Seamless Pipeline Operation. 2015
40. Low-Distortion Wideband Delta-Sigma ADCs With Shifted
Loop Delays. 2015
41. Multirate Charge-Domain Filter Design for RF-Sampling Multi-
Standard Receiver. 2015
42. Theory and Design of a Quadrature Analog-to-Information
Converter for Energy-Efficient Wideband Spectrum Sensing. 2015
43. A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery
With Jitter Suppression. 2015
44. A Heterogeneous Reconfigurable Cell Array for MIMO Signal
Processing. 2015
45.
Efficient Sub quadratic Space Complexity Architectures for
Parallel MPB Single- and Double-Multiplications for All
Trinomials Using Toeplitz Matrix-Vector Product
Decomposition.
2015
46. Fine-Grained Critical Path Analysis and Optimization for Area-
Time Efficient Realization of Multiple Constant Multiplications. 2015
47. Low-Latency High-Throughput Systolic Multipliers Over
GF(2m) for NIST Recommended Pentanomials.
2015
Any queries contact
9941928222/8680802110
29,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43556664
Mobile : +91-8680802110
www.temasolution.com
48. SoC-Based Architecture for an Ultrasonic Phased Array With
Encoded Transmissions.
2015
49. A Hopf Resonator for 2-D Artificial Cochlea: Piecewise Linear
Model and Digital Implementation. 2015
50. A Low Power and High Sensing Margin Non-Volatile Full
Adder Using Racetrack Memory. 2015
