INPU

T-OUTP

UT

ORGANIZAT

ION

61 62 Peripheral Devices

bull Every time a key is depressed the terminal sends a binary coded character to the computer When input information is transferred to the processor via a keyboard the processor will be idle most of time while waiting for info To arrive

bull Devices are said to be connected online that are under the direct control of the computer These devices are designed to read information into or out of memory unit when CPU gives a command Input or output devices connected to the computer are also called peripherals

bull Common peripherals are keyboard displays units and printers

bull Peripherals that provide auxiliary storage for system are magnetic disk

63 INTERFACE ndash Difference between computer and peripherals

A conversion of signal values may be required

raquo CPU (Electronics) HDD (Electromechanical and Electromagnet)

A synchronization mechanism may be needed

raquo The data transfer rate of peripherals is usually slower than the transfer rate of the CPU

Data codes and formats in peripherals differ from the word format in the CPU and Memory

The operating modes of peripherals are different from each other 4 modes

raquo Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU

bull Special hardware components between the CPU and peripherals

bull Supervise and Synchronize all input and output transfers

IO BUS AND INTERFACE MODULES

IO BUS VERSUS MEMORY BUS

Computer buses can be used to communicate with memory and IO

1) Use two separate buses one for memory and the other for IO

bull IO Processor separate memory bus and IO bus

2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO

bull IN OUT IO Instruction

bull MOV or LD Memory readwrite Instruction

3) Use one common bus for memory and IO with common control lines Memory

Mapped IO

bull MOV or LD IO and Memory readwrite Instruction

4 IO port Data port A Data port B ControlStatusbull8255 PIO ( port A B C ControlStatus )Address Decode bullCS RS1 RS0

Exam

ple

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

61 62 Peripheral Devices

bull Every time a key is depressed the terminal sends a binary coded character to the computer When input information is transferred to the processor via a keyboard the processor will be idle most of time while waiting for info To arrive

bull Devices are said to be connected online that are under the direct control of the computer These devices are designed to read information into or out of memory unit when CPU gives a command Input or output devices connected to the computer are also called peripherals

bull Common peripherals are keyboard displays units and printers

bull Peripherals that provide auxiliary storage for system are magnetic disk

63 INTERFACE ndash Difference between computer and peripherals

A conversion of signal values may be required

raquo CPU (Electronics) HDD (Electromechanical and Electromagnet)

A synchronization mechanism may be needed

raquo The data transfer rate of peripherals is usually slower than the transfer rate of the CPU

Data codes and formats in peripherals differ from the word format in the CPU and Memory

The operating modes of peripherals are different from each other 4 modes

raquo Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU

bull Special hardware components between the CPU and peripherals

bull Supervise and Synchronize all input and output transfers

IO BUS AND INTERFACE MODULES

IO BUS VERSUS MEMORY BUS

Computer buses can be used to communicate with memory and IO

1) Use two separate buses one for memory and the other for IO

bull IO Processor separate memory bus and IO bus

2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO

bull IN OUT IO Instruction

bull MOV or LD Memory readwrite Instruction

3) Use one common bus for memory and IO with common control lines Memory

Mapped IO

bull MOV or LD IO and Memory readwrite Instruction

4 IO port Data port A Data port B ControlStatusbull8255 PIO ( port A B C ControlStatus )Address Decode bullCS RS1 RS0

Exam

ple

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

63 INTERFACE ndash Difference between computer and peripherals

A conversion of signal values may be required

raquo CPU (Electronics) HDD (Electromechanical and Electromagnet)

A synchronization mechanism may be needed

raquo The data transfer rate of peripherals is usually slower than the transfer rate of the CPU

Data codes and formats in peripherals differ from the word format in the CPU and Memory

The operating modes of peripherals are different from each other 4 modes

raquo Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU

bull Special hardware components between the CPU and peripherals

bull Supervise and Synchronize all input and output transfers

IO BUS AND INTERFACE MODULES

IO BUS VERSUS MEMORY BUS

Computer buses can be used to communicate with memory and IO

1) Use two separate buses one for memory and the other for IO

bull IO Processor separate memory bus and IO bus

2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO

bull IN OUT IO Instruction

bull MOV or LD Memory readwrite Instruction

3) Use one common bus for memory and IO with common control lines Memory

Mapped IO

bull MOV or LD IO and Memory readwrite Instruction

4 IO port Data port A Data port B ControlStatusbull8255 PIO ( port A B C ControlStatus )Address Decode bullCS RS1 RS0

Exam

ple

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

IO BUS AND INTERFACE MODULES

IO BUS VERSUS MEMORY BUS

Computer buses can be used to communicate with memory and IO

1) Use two separate buses one for memory and the other for IO

bull IO Processor separate memory bus and IO bus

2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO

bull IN OUT IO Instruction

bull MOV or LD Memory readwrite Instruction

3) Use one common bus for memory and IO with common control lines Memory

Mapped IO

bull MOV or LD IO and Memory readwrite Instruction

4 IO port Data port A Data port B ControlStatusbull8255 PIO ( port A B C ControlStatus )Address Decode bullCS RS1 RS0

Exam

ple

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

IO BUS VERSUS MEMORY BUS

Computer buses can be used to communicate with memory and IO

1) Use two separate buses one for memory and the other for IO

bull IO Processor separate memory bus and IO bus

2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO

bull IN OUT IO Instruction

bull MOV or LD Memory readwrite Instruction

3) Use one common bus for memory and IO with common control lines Memory

Mapped IO

bull MOV or LD IO and Memory readwrite Instruction

4 IO port Data port A Data port B ControlStatusbull8255 PIO ( port A B C ControlStatus )Address Decode bullCS RS1 RS0

Exam

ple

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

EXAMPLE OF IO INTERFACE

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

64 Data Transfer Techniques

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

ASYNCHRONOUS DATA TRANSFER

Synchronous Data Transfer

bull All data transfers occur simultaneously during the occurrence of a clock pulse

bull Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

bull Internal timing in each unit (CPU and Interface) is independent

bull Each unit uses its own private clock for internal registers

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

STROBE

Strobe Control signal to indicate the time at which data is being transmitted

1) Source-initiated strobe 2) Destination-initiated strobe

Destin

atio

n-in

itiate

d stro

be

Sourc

e-i

nit

iate

d s

trobe

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

HANDSHAKINGbull For data transfer between two computers the sending and receiving

speeds on both ends are often different Therefore a mechanism is needed to make sure that the sender does not send a new byte before the previously sent byte is received by the receiver

bull Even when the sender and receiver operate at the same speed the sender may still want to know whether the receiver has indeed received the information Handshaking provides a mechanism for addressing this issue

bull Handshaking usually uses two additional hardware lines one is called ldquostroberdquo and the other is called ldquoacknowledgerdquo The sender provides the signal to the strobe line and the receiver provides the signal to the acknowledge line

bull Handshaking can be used in both parallel data transfer and serial data transfer

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

ASYNCHRONOUS SERIAL TRANSFER

Synchronous transmission

raquo The two unit share a common clock frequency

raquo Bits are transmitted continuously at the rate dictated by the clock pulses

1048698 Asynchronous transmission

raquo Special bits are inserted at both ends of the character code

raquo Each character consists of three parts

1048698 1) start bit always ldquo0rdquo indicate the beginning of a character

1048698 2) character bits data

1048698 3) stop bit always ldquo1rdquo

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

ASYNCHRONOUS TRANSMISSION RULES NO PARITY

raquo When a character is not being sent the line is kept in the 1-state

raquoThe initiation of a character transmission is detected from the start bit which is

always ldquo0rdquo

raquoThe character bits always follow the start bit

raquo After the last bit of the character is transmitted a stop bit is detected when the line

returns to the 1-state for at least one bit time (stop bits 1 15 2)

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Asynchronous Communication Interface

bull On Board

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Mode of Transfer

bull Information transferred from central computer into an external device initiates in memory unit CPU only executes IO instructions and may accept data temporarily but the ultimate source or destination is memory unit Data transfer between central computer and IO devices may be handled in variety of modes

bull Data transfer to and from peripherals may be done in either of three modes

Programmed IO Interrupt ndash initiated IO Direct Memory Access (DMA)

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

bull Binary information received from an external device is usually stored in memory

bull Information transferred from the central computer into an external device also is originally from the memory

bull Data transfer between the central computer and input and output devices may be handled in a variety of modes

Introduction

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Programmed IObull These operations are a results of IO instructions

written in the computer program Data transfer is

initiated by an instruction in the program

bull Usually the data transfer data between CPU register

and peripheral device Other instructions are used to

transfer data transfer data between CPU and memory

bull The peripheral has to be constantly monitored Once a

data transfer is initiated the CPU is required to monitor

the interface to see when a transfer can again be made

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Applications of programmed IO method Useful in small low speed computers

Used in systems that are dedicated to monitor a

device continuously

Used in the data register

Used to check the status of the flag bit and branch

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

bull in this scheme CPU may allow devices to send a signal when input is waiting to be processed The signal is used to interrupt the CPU

bull Interrupt signal are seen directly (using hardware) to micro-processor which may or may not ignore interrupt request When request is granted CPU will suspend its current program execution execute an interrupt handler program and then resume execution of the interrupted program

Interrupt initiated IO

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

bull Interrupted initiated IO can be avoided by using an

interrupt facility and special commands to inform the

interface to issue an interrupt request signal when the

data are available from the device

bull Meanwhile CPU can proceed to execute another program

The interfaces keeps monitoring the device

bull When the interface determines that the device is ready for

data transfer it generates an interrupt request to the

computer

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Service routines of Interrupt initiated IO

Service routines of interrupt initiated IO can be

chosen in two ways

Vectored interrupt

Non-vectored interrupt

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Direct Memory Access (DMA)

bull The interface transfer data into and out of the memory unit

through the memory bus

bull The CPU initiates the transfer of supplying the interface

with the starting address and the number of words needed

to be transferred and then proceed to execute other tasks

bull When the request is granted by the memory controller the

DMA transfer the data directly into memory The CPU delays

its memory access operation to allow the direct memory IO

transfer

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

IO Processorbull Many computers combines the interface logic with the requirements for direct

memory access into one unit and call it an IO processor The IOP can handle many

peripherals through a DMA and interrupt facility The computer is divided into

three separate modules in such a system

Memory unit

CPU

IOP

bull CPU is the master while the IOP is a slave processor The CPU performs the tasks of

initiating all operations

bull The operations include

Starting an IO transfer

Testing IO status conditions needed for making decisions on various IO activities

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

IO Interrupts

Priority

- Determines which interrupt is to be served first

when two or more requests are made simultaneously

- Also determines which interrupts are permitted to

interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while

servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices (interrupt sources)

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts

all the interrupt requests to determine the highest priority request

- Fast since identification of the highest priority

interrupt request is identified by the hardware

- Fast since each interrupt source has its own interrupt vector to access

directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

One stage of the daisy chain priority arrangement

PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1

Interrupt Request from any device(gt=1) -gt CPU responds by INTACK lt- 1 -gt Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1 and it blocks INTACK to propagate to the next device

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

Serial hardware priority function Interrupt Request Line

- Single common line Interrupt Acknowledge Line

- Daisy-Chain

S

R

QInterruptrequest

from device

PIPriority in

RF

Delay

Vector address

VAD

POPriority out

Interrupt request to CPU

Enable

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

PARALLEL PRIORITY INTERRUPT

IEN Set or Clear by instructions ION or IOFIST Represents an unmasked interrupt has occurred INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Maskregister

INTACKfrom CPU

Priorityencoder

I0

I1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt whenmore than one interrupts take place

Priority Encoder Truth table

1 d d d0 1 d d0 0 1 d0 0 0 10 0 0 0

I0 I1 I2 I3

0 0 10 1 11 0 11 1 1d d 0

x y IST

x = I0 I1y = I0 I1 + I0rsquo I2rsquo

(IST) = I0 + I1 + I2 + I3

Inputs Outputs

Boolean functions

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

At the end of each Instruction cycle

- CPU checks IEN and IST

- If IEN IST = 1 CPU -gt Interrupt Cycle

INTERRUPT CYCLE

SP SP - 1 Decrement stack pointerM[SP] PC Push PC into stackINTACK 1 Enable interrupt acknowledgePC VAD Transfer vector address to PCIEN 0 Disable further interruptsGo To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

INTERRUPT SERVICE ROUTINE

Initial and Final OperationsEach interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system

Initial Sequence [1] Clear lower level Mask reg bits [2] IST lt- 0 [3] Save contents of CPU registers [4] IEN lt- 1 [5] Go to Interrupt Service Routine

Final Sequence [1] IEN lt- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg bits [5] Restore return address IEN lt- 1

address Memory

JMP PTR

JMP RDR

JMP KBD

JMP DISK0

1

2

3

IO service programs

Program to servicemagnetic disk

Program to serviceline printer

Program to servicecharacter reader

Program to servicekeyboard

DISK

PTR

RDR

KBD

255256

750

256750

Stack

Main program

current instr749KBDinterrupt

2

VAD=00000011 3

4

Diskinterrupt

5

6

7

8

9 10

11

1

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

DIRECT MEMORY ACCESS

High-impedence(disabled)

when BG isenabled

CPU bus signals for DMA transfer

Block of data transfer from high speed devices Drum Disk Tape DMA controller - Interface which allows IO transfer directly between

Memory and Device freeing CPU for other tasks CPU initializes DMA Controller by sending memory address and the block size(number of words)

Address bus

Data bus

Read

Write

ABUSDBUS

RDWR

Bus request

Bus granted

BR

BGCPU

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

Block Diagram Of DMA Controller

Address bus

Data bus

DMA select

Register select

Read

Write

Bus request

Bus grant

Interrupt

DS

RS

RD

WR

BR

BG

Interrupt

Data busbuffers

Address busbuffers

Address register

Word count register

Control register

DMA request

DMA acknowledge to IO device

Controllogic

Inte

rnal

Bu

s

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

DMA IO OPERATIONStarting an IO - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command

Upon receiving a GO Command DMA performs IOoperation as follows independently from CPU

Input [1] Input Device lt- R (Read control signal) [2] Buffer(DMA Controller) lt- Input Byte and assembles the byte into a word until word is full [4] M lt- memory address W(Write control signal) [5] Address Reg lt- Address Reg +1 WC(Word Counter) lt- WC - 1 [6] If WC = 0 then Interrupt to acknowledge done else go to [1]

Output [1] M lt- M Address R M Address R lt- M Address R + 1 WC lt- WC - 1 [2] Disassemble the word [3] Buffer lt- One byte Output Device lt- W for all disassembled bytes [4] If WC = 0 then Interrupt to acknowledge done else go to [1]

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

CYCLE STEALING

While DMA IO takes place CPU is also executing instructions

DMA Controller and CPU both access Memory -gt Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access - Priority System

Memory accesses by CPU and DMA Controller are interwoven with the top priority given to DMA Controller

-gt Cycle Stealing

Cycle Steal

- CPU is usually much faster than IO(DMA) thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles CPU remains idle - For those slow CPU DMA Controller may steal most of the memory

cycles which may cause CPU remain idle long time

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

DMA TRANSFER

BG

BRCPU

RD WR Addr Data

Interrupt

Random-accessmemory unit (RAM)

RD WR Addr Data

BR

BG

RD WR Addr Data

Interrupt

DS

RS DMAController

IOPeripheral

deviceDMA request

DMA ack

Read control

Write control

Data bus

Address bus

Addressselect

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

INPUTOUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability that communicates with IO devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the IO devices and perform data transfer operations - CPU initiates the channel by executing an channel IO class instruction and once initiated channel operates independently of the CPU

PD PD PD PD

Peripheral devices

IO bus

Input-outputprocessor

(IOP)

Centralprocessingunit (CPU)

Memoryunit

Me

mo

ry B

us

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations

CHANNEL CPU COMMUNICATION

Send instructionto test IOPpath

If status OK then sendstart IO instruction

to IOP

CPU continues withanother program

Transfer status wordto memory

Access memoryfor IOP program

Conduct IO transfersusing DMA

Prepare status report

IO transfer completedInterrupt CPU

Request IOP status

Transfer status wordto memory locationCheck status word

for correct transfer

Continue

CPU operations IOP operations