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POLITECNICO DI MILANO
Blanket Team
BlanketBlanketReconfigurable architecture and
(IP) runtime reconfiguration support in
Dynamic Reconfigurability in Embedded System Design
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OutlineOutline
Rationale
Objectives
Project Description
Subprojects:YaRA, HARPE, ReCPU, SCAR, IPs
Blanket in DRESD
General information
RationaleRationaleFlexibility: many emerging products in communication, computing and consumer electronics demand that their functionality remains flexible also after the system has been manufactured.
Support of new standards, e.g. in media processingAddition of new features
Cost reduction and reusability: While a ready-made FPGA can be bought for $500, an application-specific IC, or ASIC, can cost anywhere from $4 million to $50 million. “If you make a mistake on an FPGA, hey, you just reprogram it. “ Dean Collins, deputy director of DARPA's Microsystems Technology Office and program manager for the Trust in IC initiative.
Performance and runtime customization: reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Therefore it is possible to apply reconfigurable solutions to systems such as:
biomedical implants i.e., an artificial art controltelecommunications i.e., adaptive intelligent routersMoreover: intelligent nanorobot control, artificial audio and vision, intelligent transducers at bio-electronic interfaces,…
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ObjectivesObjectives
Exploit dynamic reconfigurability for different target reconfigurable architectures
Design innovative applicative solutions, with the corresponding architecture, towards real world needs
Explore novel architectural paradigms e.g, DNA computing, bio-inspired system
Increase the reconfiguration performance via novel techniques, i.e. runtime reconfigurable cores relocation
Project Project DescriptionDescription
Blanket is a project related to the definition of novel reconfigurable architectures
Blanket can be seen as organized in mainly three different parts:
Generic reconfigurable architectureYaRA (SoC, MultiFPGA)HARPE (Multicore)
Application specific reconfigurable architectureReCPU (Regular Expression CPU)SCAR (a sort of reconfigurable ASIP)
IP design to enhance the reconfiguration capabilities or to effectively use the reconfiguration at runtime
DRC, BiRF, C*,...
YaRAYaRA
YaRA: Yet another Reconfigurable Architecture
The basic reconfigurable architecture defineda Static area: a basic Harvard architecturea Reconfigurable area: a device area composed of several reconfigurable regions
YaRA v1: 1D, Whishbone BUS-basedYaRA v2: 2D,CoreConnect-based
HARPEHARPE
HARPE: a HARvard-based Processing Element tailored for partial dynamic reconfigurable architectures
marBram: a framework for the creation of memory configuration bitstreamsPropose a stand-alone processing element (PE)
Harvard ArchitectureSoft-Processor
Suits reconfigurable architecturesEasily Configurable
User-LogicSoftware (not supported by Xilinx tools)
Bitstream FileBitstream File
ReCPUReCPU
ReCPU: a new parallel and pipelined architecture for regular expression matchingRegular Expressions (RE) as a programming language
A RE is a sequence of instructions to be executed by the ReCPU processor
SCARSCAR
SCAR: Soft Core Adaptable aRchitectureNaHA: Nios adaptable Harvard-based ArchitectureWhat’s next: Leon, MicroBlaze...
Propose an adaptable Harvard-based architecture able to meet at the best the specific needs of an application that has to be executed on a reconfigurable device
IPsIPs
DRC: DRESD/Dynamic Reconfiguration ControllerAdaptable self-reconfiguration controllers
BiRF: Bitstream Relocation FilterIP-Core used to implement runtime bitstream relocationRelocation solution suitable for different target architecture (BiRF, BiRF2, …)
C*: all the runtime reconfiguration support in a unique pipelined reconfiguration controller
Blanket in DRESDBlanket in DRESDBlanket and Caronte
marBram: a framework for the creation of memory configuration bitstreamsLimboWARE: postpone the decision of whether executing a task in HW or in SW moving it at run-timeVIRGIL: codesing frameworkDRCGen: automatic tool to define the best DRC according to the working scenario
Blanket and CITiESPEReIRA: active reconfigurable functional unitYaRA (v3): a NoC based reconfigurable architecture
Blanket and HERAYaRA (v2+): a 2D tile based reconfigurable architecture to implement online evolution
Blanket and OSyRISOS and architecture
Blanket and PolarisC* and BiRF: IPs for runtime relocation
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General InformationGeneral Information
Webpage
www.dresd.org/blanket
Mailing List
ContactTo have more information regarding Polaris:
For a complete list of information on how to contact us:www.dresd.org/contact_blanket