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Lecture 26a:Software Environments
for Embedded SystemsPrepared by: Professor Kurt Keutzer
Computer Science 252, Spring 2000
With contributions from:
Jerry Fiddler, Wind River Systems,
Minxi Gao, Xiaoling Xu, UC BerkeleyShiaoje Wang, Princeton
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SW: Embedded Software Tools
CPU
ROM
RAM
A
SIC
ASIC
RTOSa.out
Application
software
simulator
compiler applicationsource
code
debugger
US
ER
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Another View of Microprocessor Architecture
Lets look at current architectural evolution from the standpoint ofthe software developers , in particular Jerry Fiddler
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Fiddlers Predictions for the Next Ten
Years (2010)End of the Age of the PC
Lots of Exciting Applications
Development Will Continue To Be HardG Even as we and our competitors continue to make
incredible efforts
Chips - No predictionsMEMS / Nano-technology & Sensors Will Impact Us
J. Fiddler - WRS
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Fundamental Principles
Computers are, and will be, everywhere
The world itself is becoming more intelligent
Our infrastructure will have major software contentMost of our access to information will be through embedded
systems
Economics will inexorably drive deployment of embeddedsystems
The Internet is one important factor in this trend
Reliability is a critical issue
EVERY tech and mfg. business will need to become good atembedded software
J. Fiddler - WRS
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What Will Be Embedded in Ten Years?
Everything That is Now Electro-Mechanical
Machines (Nano-Machines)
Analog SignalsAnything that communicates
Lots of stuff in our cars
Our BodiesG Today - PacemakersG Soon - De-Fibrillators, Insulin DispensersG We can all be the $6M Person, for a lot cheaper
All sorts of interfaces
G Speech, DNI, etc.
J. Fiddler - WRS
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Embedded Microprocessor Evolution
19891989 19931993 19951995 19991999
> 500k transistors1 - 0.8 33 mHz
2+M transistors0.8 - 0.5
75 - 100 mHz
5+M transistors0.5 - 0.35
133 - 167 mHz
22+M transistors0.25 - 0.18
500 - 600 mHz
Embedded CPU cores are getting smaller; ~ 2mm 2 for up to 400 mHz
G Less than 5% of CPU sizeHigher Performance by:
G Faster clock, deeper pipelines, branch prediction, ...
Trend is towards higher integration of processors with:G Devices that were on the board now on chip: system on a chipG Adding more compute power by add-on DSPs, ...G Much larger L1 / L2 caches on silicon
J. Fiddler - WRS
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680x0CPU32
PowerPC
29k680x0CPU32
80x86SPARC
MIPS R3ki960
Microprocessor Chaos
ST 20M32 R/D
StrongARMARM
SH-DSPSH 4
MCORE
19801980 1990 1996 1998
68000
80x86MIPS 3k/4k/5k
SPARCSH 1/2/3
29kRAD 6k
Siemens C16x
NEC V8xxPARISC
i960563xx
680x0CPU32
PowerPC80x86
MIPS 3k/4k/5kSPARCSH 1/2/3
29kRAD 6k
Siemens C16x
NEC V8xxPARISC
i960563xx
J. Fiddler - WRS
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A Challenging Environment
Numerous Microprocessor ArchitecturesNumerous Microprocessor ArchitecturesDerivative ProcessorsDerivative Processors
ApplicationApplication --Specific CPUsSpecific CPUsSystems On A ChipSystems On A Chip
Expanding Functional DemandsExpanding Functional DemandsOf Embedded ApplicationsOf Embedded Applications
And keep itAnd keep itsmall, stupid!small, stupid!
J. Fiddler - WRS
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New Hardware Challenges SoftwareDevelopment
More & More ArchitecturesG User-Customizable processors
More Power Demands More Software FunctionalityG Software is not following Moores law (yet)
System-on-a-chip
DSP
J. Fiddler - WRS
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Embedded Software Crisis
Cheaper, more powerfulCheaper, more powerfulMicroprocessorsMicroprocessors
MoreMoreApplicationsApplications
IncreasingIncreasingTimeTime --toto --marketmarketpressurepressure
Bigger, More ComplexBigger, More Complex
ApplicationsApplications
EmbeddedEmbeddedSoftwareSoftware
CrisisCrisis
J. Fiddler - WRS
J. Fiddler - WRS
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SW: Embedded Software Tools
CPU
ROM
RAM
A
SIC
ASIC
RTOSa.out
Application
software
simulator
compiler applicationsource
code
debugger
USER
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Outline on RTOS
Introduction
VxWorks
G General descriptionG SystemG Supported processors
G DetailsG KernelG Custom hardware supportG Closely coupled multiprocessor
supportG Loosely coupled multiprocessor
support
pSOS
eCos
Conclusion
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Embedded Development: Generation 0
Development: Sneaker-net
Attributes:G No OSG Painful!G Simple software only
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Embedded Development: Generation 1
Hardware: SBC, minicomputer
Development: Native
Attributes:G Full-function OS
G Non-ScalableG
Non-PortableG TurnkeyG Very primitive
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Embedded Development: Generation 2
Hardware: Embedded
Development: Cross, serial line
AttributesG KernelG Originally no file sys, I/O, etc.G No development environmentG No network G Non-portable, in assembly
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Embedded Development: Generation 3
Hardware: SBC, embedded
Development: Cross, EthernetG Integrated, text-based, Unix
AttributesG Scalable, portable OS
G Includes network, file & I/O sys, etc.G Tools on target
G Network requiredG Heavy target required for development
G Closed development environment
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Embedded Development: Generation 4
Hardware: Embedded, SBC
Development: Cross
G Any tool - Any connection - Any targetG Integrated GUI, Unix & PC
Attributes
G Tools on hostG No target resources requiredG Far More Powerful Tools (WindView, CodeTest, )
G Open dev. environment, published API
G Internet is part of dev. environmentG Support, updates, manuals, etc.
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Embedded Development: Generation5???
Super-scalable
Communications-centric
Virtual application platformG Java?
Multi-media
Way-cool development environmentG Much easier to create, debug & re-use codeG Easy for non-programmers to contribute
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The RTOS Evolution
*Percent of total software supplied by RTOS vendor in a typical embedded device
1980 1990 1996 1998
10%*Kernel30%*
KernelNetworkingFile System
75%*
KernelNetworkingFile System
MultiprocessingMemory Management
WindNetX Windows
Application
Application
Application
Application
90%*
KernelNetworkingFile System
MultiprocessingFault Tolerance
Distributed ObjectsAdvanced Networking
Advanced InterconnectJava
Browser / GUI
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Introduction to RTOS
Wind River Systems Inc. VxWorks
http://www.wrs.com
Integrated Systems Inc. pSOS
http://www.isi.com
Cygnus Inc. => RedHat eCos
http://www.cygnus.com => www.redhat.com
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22VxWorks
VxWorks
Multiprocessing supportGraphics Internet support
POSIX LibraryJava support File system
WindNet Networking
Core OS
Wind Microkernel
Real-Time Embedded Applications
VxWorks 5.4 Scalable Run-Time System
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Supported Processors
PowerPC
68K, CPU 32
ColdFire
MCORE
80x86 and Pentium
i960
ARM and Strong ARM
MIPS
SH
SPARCNEC V8xx
M32 R/D
RAD6000
ST 20
TriCore
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24VxWorks
Wind microkernel
Task managementG multitasking, unlimited number of tasksG preemptive scheduling and round-robin
scheduling(static scheduling)G fast, deterministic context switchG 256 priority levels
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Wind microkernel
Fast, flexible inter-task communicationG binary, counting and mutual exclusion semaphores
with priority inheritanceG message queueG POSIX pipes, counting semaphores, message
queues, signals and schedulingG control socketsG shared memory
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Wind microkernel
High scalability
Incremental linking and loading of components
Fast, efficient interrupt and exception handling
Optimized floating-point support
Dynamic memory managementSystem clock and timing facilities
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27VxWorks
``Board Support Package
BSP = Initializing code for hardware device + device driverfor peripherals
BSP Developers Kit
BSP
Device dependent codeHardware
independentcode
Processordependent
code
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28VxWorks
VxMP
A closely coupled multiprocessor support accessory forVxWorks.
Capabilities:G Support up to 20 CPUsG Binary and counting semaphoresG FIFO message queuesG Shared memory pools and partitionsG VxMP data structure is located in a shared memory area
accessible to all CPUsG Name service (translate symbol name to object ID)G User-configurable shared memory pool sizeG Support heterogeneous mix of CPU
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VxMP
Hardware requirements:G Shared memoryG Individual hardware read-write-modify mechanism across
the shared memory busG CPU interrupt capability for best performanceG Supported architectures:
G
680x0 and 683xxG SPARCG SPARCliteG PPC6xxG MIPSG i960
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30VxWorks
VxFusion
VxWorks accessory for loosely coupled configurations and standardIP networking;
An extension of VxWorks message queue, distributed messagequeue.
Features:G Media independent design;G
Group multicast/unicast messaging;G Fault tolerant, locale-transparent
operations;G Heterogeneous environment.
Supported targets:G Motorola: 68K, CPU32, PowerPCG Intel x86, Pentium, Pentium Pro
App1 App2
VxFusion
Adapter Layer
Transport
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31pSOS
pSOS
pSOS+ Kernel
Memory
Management
POSIX
LibraryBSPsI/O system
Loader Debug C/C++ File System
pSOS 2.5
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32pSOS
Supported processors
PowerPC
68K
ColdFireMIPS
ARM and Strong ARM
X86 and Pentium
i960
SH
M32/R
m.core
NEC v8xxST20
SPARClite
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33pSOS
pSOS+ kernel
Small Real Time multi-tasking kernel;
Preemptive scheduling;
Support memory region for different tasks;
Mutex semaphores and condition variables
(priority ceiling)No interrupt handling is included
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34pSOS
Board Support Package
BSP = skeleton device driver code + code for low-level system functions each particular devices
requires
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35pSOS
pSOS+m kernel
Tightly coupled or distributed processors;
pSOS API + communication and coordination functions;
Fully heterogeneous;Connection can be any one of shared memory, serial or
parallel links, Ethernet implementations;
Dynamic create/modify/delete OS object;Completely device independent
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36eCos
eCos
ISO C Library Native Kernel C API ITRON 3.0 API
Internal Kernel API
Kernel
pluggable schedulers, mem alloc,synchronization, timers, interrupts,
threads
HAL
D e v
i c e
D r
i v e r s
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37eCos
Supported processors
Advanced RISC Machines ARM7
Fujitsu SPARClite
Matsushita MN10300
Motorola PowerPC
Toshiba TX39
Hitachi SH3
NEC VR4300MB8683x series
Intel strong ARM
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38eCos
Kernel
No definition of task, support multi-thread
Interrupt and exception handling
Preemptive scheduling: time-slice scheduler, multi-levelqueue scheduler, bitmap scheduler and priorityinheritance scheduling
Counters and clocksMutex, semaphores, condition variable, message box
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39eCos
Hardware Abstraction Layer
Architecture HAL abstracts basic CPU, including:G interrupt deliveryG context switchingG CPU startup and etc.
Platform HAL abstracts current platform, includingG platform startupG timer devicesG I/O register accessG interrupt control
Implementation HAL abstracts properties that lie between the above,G
architecture variantsG on-chip devices
The boundaries among them blurs.
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Summary on RTOS
VxWorks pSOS eCos
Task Y Y Only Thread
Scheduler Preemptive, static Preemptive PreemptiveSynchronization mechanism No condition variable Y Y
POSIX support Y Y Linux
Scalable Y Y Y
Custom hw support BSP BSP HAL, I/O package
Kernel size - 16KB -
Multiprocessor support VxMP/ VxFusion(accessories)
PSOS+mkernel
None
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41VxWorks
Recall the ``Board Support Package
BSP = Initializing code for hardware device + device driverfor peripherals
BSP Developers Kit
BSP
Device dependent codeHardwareindependentcode
Processordependentcode
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Introduction to Device Drivers
What are device drivers?G Make the attached device work.G Insulate the complexities involved in I/O handling.
Application
Device driver
Hardware
RTOS
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Proliferation of Interfaces
New ConnectionsG USBG
1394G IrDAG Wireless
New ModelsG JetSendG JiniG HTTP / HTML / XML / ???G Distributed Objects (DCOM, CORBA)
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Leads to Proliferation of Device Drivers
Courtesy - Synopsys
h
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Device Driver Characterization
Device Drivers FunctionalitiesG initializationG
data accessG data assignmentG interrupt handling
D i h
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Device Characterization
Block devices
G fixed data block sizes devices
Character devices
G byte-stream devices
Network deviceG manage local area network and wide area network
interconnections
I/O P i Ch t i ti
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I/O Processing Characteristics
InitializationG make itself known to the kernelG
initialize the interrupt handlingG optional: allocate the temporary memory for device
driverG initialize the hardware device
Front-End ProcessingG initiation of an I/O request
Back-End ProcessingG handles the completion of I/O operations
C i l R
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Commercial Resources
Aisys DriveWay 3DEG Motorola MPC860, MC68360, MC68302, AMD E86,
Philips XA, 8C651, PIC 16/17
Stenkil MakeAppG Hitachi H8, SH1, SH3, SH7x, HCAN
Intels ApBuilder
Motorola MCUnit
GO DSP Code ComposerG TI DSPs
CoWare
Aysis 3DE DriveWay Features
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Aysis 3DE DriveWay Features
Extensive documentation: KB help along the way asdetailed as a chip manual: traffic.ext, traffic.dwp
CNFG for configuring the chip such as memory and clock.Gives warning if necessary
Can generate test function
Can insert user code
One file for each peripheral
DriveWay Design Methodology
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DriveWay Design Methodology
GUI
.DLL K.B.
Codegenerator
.DWP
Outputfiles
Chipspecific
User dataLittle generation
more manipulation
Manipulationof K.B.database
K B Database
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K.B. Database
A specific K.B. per chip family
Family of chips
G chipG peripherals
functional objects (timer, PWM counter) functions physicals (register setting, values, clock rate) actual code
DriveWay Builder
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DriveWay Builder
Add chip
Add peripheral
Create skeleton, link to other thins such as GUICode reuse in adding a new chip in an existing family, e.g.,
use code in MPC 860 for MPC 821
Easy to create infrastructure but specifics has to be written
About the code generator (1)
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About the code generator (1)
Cut and paste K.B. database
Areas where we can use automation for device driver
generation:G model user specificationG extract useful information for drivers from HDL
description of the chipG MAP registersG interrupt
About the code generator (2)
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About the code generator (2)
Why is Aysis not using automation?G
Commercial efficiencyG e.g., easy to capture user specification from the
GUI rather than using a model such as UML orstate machine
G HDL code too low level, hard to extract information
CoWare Interface Synthesis
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CoWare Interface Synthesis
System suggests hardware/software interface protocolsG Handshaking, memory mapped I/O, interrupt scheme,
DMA
Designer selects communication protocols & memory
System synthesizes efficient device drivers and glue logic
Hardware
Glue Logic
Software
DeviceDriver
Interface Synthesis Example: Memory Mapped I/O
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Processor
compiled on processor
SW
Port = value;
HWPort
MemoryAddress FFA3
Glue Logic
SW
DeviceDriver
GlueLogic
HW
Device Driver
SW
*FFA3 = value;*FFA3
HW
Interface Synthesis Example: Memory Mapped I/O
SW: Embedded Software Tools
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SW: Embedded Software Tools
CPU
ROM
RAM
ASIC
ASIC
RTOSa.out
Application
software
simulator
compiler applicationsource
code
debugger
USE
R
ASIC Value Proposition
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S C Va ue opos t o
RAM CRAM
DSPCOREASIC
LOGIC
S/PDMA
20% area decrease in ASIC portion 25% higher performance move to higher level - HDL description at RTL
The Importance of Code Size
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p
Based on base 0.18 implementation plus code RAM or cacheXtensa code ~10% smaller than ARM9 Thumb, ~50% smaller than MIPS-Jade, ARM9 and ARCARM9-Thumb has reduced performanceRAM/cache density = 8KB/mm 2
A r e a v s . P r o g r a m I n s t r u c t i o n s
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 1000 2000 3000 4000 5000 6000 7000 8000Program Size (Instructions)
P r o c e s s o r
+ C o
d e
R A M
m m
2
Xtensa MIPS-4Kc ARC ARM9 ARM9-Thumb
Killian- Tensilica
SW Compiler Value Proposition
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p p
RAM CRA
M
DSP
CORE
ASICLOGIC
S/P
DMA
20% area decrease over ASIC portion
20% area decrease in RAM portion 25% higher performance move to higher level - C rather than assembler
Memory? StrongARM Processor
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y g
Compaq/DigitalCompaq/DigitalStrongARMStrongARM
Compiler Support
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p pp
BUT, few companies focused on compiler support forembedded systems:
G Cygnus => RedHatG Tartan => TIG Green Hills
Why?
Bad ``buying behaviors few seats, low ASPs
Current Status on Compiler Support
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Adequate compiler and debugger support in breadth and quality forembedded microprocessors/microcontrollers
G ARMG MIPS
G Power PCG Mot family
FromG Cygnus/RedHatG
ManufacturerG Green Hills
DSPs still poorly supportedG Tartan acquired by Texas InstrumentsG WHY????
NO support for growing generation of special purpose processors:G TMS320C80G IXP1200
Recall: Architectural Features of DSPs
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Recall: Architectural Features of DSPsData path configured for DSP
G Fixed-point arithmeticG MAC- Multiply-accumulate
Multiple memory banks and buses -
G Harvard ArchitectureG Multiple data memories
Specialized addressing modes
G Bit-reversed addressingG Circular buffers
Specialized instruction set and execution control
G Zero-overhead loopsG
Support for MACSpecialized peripherals for DSP
Example: IXP1200
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PCI Bus Unit
SDRAM MemoryUnit
SRAM MemoryUnit
IX Bus InterfaceUnit
StrongARM core
Microengine1 Microengine
2 Microengine3 Microengine
4 Microengine5 Microengine
6
SDRAM(up to 256 MB)
SRAM(up to 8 MB)
Boot ROM(up to 8 MB)
Peripherals
Ethernet MAC ATM, T1/E1 Another IXP1200
64
64
32
FIFO Bus 66 Mhz
Host CPU (optional) PCI MAC DevicesPCI Bus 66 Mhz
32
IXP1200 Network Processor
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6 micro-enginesG RISC enginesG 4 contexts/engG 24 threads total
IX Bus InterfaceG packet I/OG connect IXPs
G scalable
StrongARMG less critical tasks
Hash engineG level 2 lookups
PCI interface
SDRAMCtrl
MicroEng
PCIInterface
SRAMCtrl
SACore
MicroEng
MicroEng
MicroEng
MicroEng
MicroEng
MiniDCache
DCache
ICache
ScratchPad
SRAM
IX BusInterface
HashEngine
Summary
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Embedded software support for microcontrollers andmicroprocessors is broadly available and of adequate quality
G RTOSG Device driversG CompilersG Debuggers
Embedded software support for DSP processors is inadequate:
G Patchy support many parts lack supportG Quality poor lags hand coding by 20-100%
Embedded software support for special purpose processors oftennon-existent
Still in a ``build a hardware then write the software worldAlternatives?
ASIP/Extensible micro DESIGN FLOW
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DESIGNER
APPLICATION_1 APPLICATION_2 APPLICATION_7
ARCHITECTURE
INSTRUCTION SET
OBJECTCODE
RETARGETABLECOMPILER
APPLICATIONCODE
SIMULATIONMODEL
PERFORMANCEANALYSIS
Tensilica TIE Overview
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ConfigureBase uP
Describe newinst in TIE
Application
Processor Generator
Processor Verilog
RTL
SoftwareTools
ASICflow
Softwarecompile
uP
Mem
SoftwareGenerator
Killian- Tensilica
Tensilica TIE Design Cycle
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Develop application in C/C++
Profile and analyze
Id potential new instructions
Describe new instructions
Generate new software tools
Correct ?N Y
Run cycle-accurate ISS
Build the entire processor
Acceptable ?N
Y
Measure hardware impact
Acceptable ?N
Compile and run application
Y
Killian- Tensilica
Conclusions
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Full embedded software support for will be requirement forfuture embedded system ``platforms
Companies evolving hardware and software together willhave a significant competitive advantage
Few examples beginning to emerge- Tensilica, STMicroelectronics