Download pdf - vlsi design report

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REPORT ON

VLSI DESIGN LAB

Under the guidance of:

Dr.Ramesh Kini

Mr. Chenna Reddy

Submitted by:

DHINKAR B. 12EC107

UJJWAL DHUSIA 12EC109

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL

SRINIVASNAGAR-575025,MANGALORE,KARNATAKA,INDIA

April 2015

Contents

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0.1 MODULE-1 REPORT : CIRCUIT SIMULATION WITH NGSPICE ......................................................................... 2

0.1.1 Lab 1: MOSFET input and output characteristics with parametric sweep ................................................. 3

0.1.2 LAB 2: Spice analysis of nmos inverter ............................................................................................................... 8

0.1.3 LAB 3: Study of MOS inverter with active load - NMOS and PMOS (pseudo) .......................................... 12

0.1.4 LAB 4: Study of CMOS Inverter ........................................................................................................................... 16

0.1.5 LAB 5: Depletion MOS and I vs V characteristics of PMOS ........................................................................... 19

0.1.6 LAB 6: study of CMOS gates ................................................................................................................................. 21

0.2 MODULE-2 REPORT : LAYOUT DESIGNING WITH MAGIC .............................................................................. 30

0.2.1 Layout design for CMOS inverter ....................................................................................................................... 31

0.2.2 Layout design for CMOS 3 input NAND gate .................................................................................................... 32

0.2.3 Layout design for CMOS 3 input NOR gate ....................................................................................................... 33

0.2.4 Layout designs for CMOS OR gate ...................................................................................................................... 35

0.2.5 Layout designs for function ab+c using CMOS ans Pseudo NMOS .............................................................. 36

0.2.6 Layout design for D - Latch .................................................................................................................................. 38

0.2.7 Layout design for D - Flip Flop ............................................................................................................................ 39

0.1 MODULE-1 REPORT : CIRCUIT SIMULATION

WITH NGSPICE

Number of experiments performed : 5

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0.1.1 Lab 1: MOSFET input and output characteristics

with parametric sweep

Objective: Study the input and output characteristic of NMOS transistor. Effect of length,width,VTO,

VSB,lambda, and temperature on the behavior of transistor.

============= CODE FOR VARYING LAMBDA ==============

m1 d g 0 0 my_nmos l = .5u w = 0.5u

*sources

v_dd d 0 dc 5 v_gg g

0 dc 3

.dc v_dd 0 5 0.1 v_gg 0 3 1

*response for varying lambda

.control foreach lmda .03 .06

.09 altermod m1

LAMBDA=$lmda run end .endc

Figure 1: Id vs Vdd (curve for varying lambda)

.control

foreach iter 1 2 3

setplot dc$iter plot -

v_dd#branch end

.endc

.end

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Reason : The id vs Vdd curve is at first linear then becomes varies slowly in saturation region due to channel length modulation which should be otherwise constant.

============= CODE FOR VARYING LENGTH ==============

*nmos charactorstic

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt

m1 d g 0 0 RITSUBN1 l=1u w=0.5u v_dd

d 0 dc 5 v_gg g 0 dc 5

.dc v_dd 0 5 0.01

*response for variable width

.control foreach length 1u 2u 5u alter m1 l=$length run end plot (-

dc1.v_dd#branch) (-dc2.v_dd#branch) (-dc3.v_dd#branch)

.endc

Figure 2: Id vs Vdd (curve for varying length)

========== CODE FOR VARYING TEMPERATURE ===========

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt m0 out in Vss

0 RITSUBN1 TEMP=27

*sources

5

Vgng Vss 0 dc 0 vdd

out 0 dc 5 Vin in 0 dc

5

.dc Vin 0 5 .1

.control foreach t1 27 50

100 alter m0 TEMP =$t1

run end .endc

Figure 3: Id vs Vdd (curve for varying temperature)

======= CODE FOR VARYING THRESHOLD VOLTAGE -VTO =======

*nmos characteristics varing length("current decreases as length is increased")

*include model files


*netlist m1 drain gate 0 0 RITSUBN1 l=3u

w=0.5u

*define the sources vdd

drain 0 dc 5 vgg gate 0

dc 5

.dc vdd 0 5 0.1 vgg 0 5 1

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*Computing the response for various width( variable)

.control

foreach vth 0.5 1 3 alter m1

VTO = $vth

run end

.endc

*plotting the output for various width

.control

foreach iter 1 2 3

setplot dc$iter plot -

vdd#branch end .endc

Figure 4: Id vs Vdd (curve for vto)

===============CODE FOR VARYING Vsb===============

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt m1 drn gate s

0 cmosn l=1u w=.5u

vdd drn 0 5 vin

gate 0 5 vss s 0 0

.dc vin 0 6 .1 vss 0 3 1

.control run plot -

vdd#branch

.end

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Figure 5: Id vs Vdd (curve for varying vsb)

============== CODE FOR VARYING WIDTH ==============

*nmos characterstic


m1 d g 0 0 RITSUBN1 l=1u w=0.5u v_dd

d 0 dc 5 v_gg g 0 dc 5

.dc v_dd 0 5 0.01

*response for variable width

.control foreach wid 1.6e-6 6.4e-6 96e-6 alter m1 w=$wid run end plot (-

dc1.v_dd#branch) (-dc2.v_dd#branch) (-dc3.v_dd#branch)

.endc

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Figure 6: Id vs Vdd (curve for varying width)

0.1.2 LAB 2: Spice analysis of nmos inverter

Objective : Study the transf er function ,noise margin,effect on risetime ,falltime, propogation delay ,power and energy consumed of a MOS inverter for various L,W of the transistor,load capacitance and rise or fall time of input .

Figure 7: NMOS with resistive load

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==== CODE FOR VARYING POWER WITH CHANGING RESISTANCE ====

*nmos characteristics with passive R load

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt M1 vdd1 in 0

0 cmosn L=10U W=5U

R1 v_connect vdd1 1k v_dd1

v_connect 0 5

v_gs in 0 5

.control foreach resistance 100 1K 10K 100K

1Meg alter R1 = $resistance dc v_gs 0 5 0.1

run *plot

vdd1 end

let p1 = (v_connect*(-dc1.v_dd1#branch)) let p2 =

(v_connect*(-dc2.v_dd1#branch)) let p3 =



(v_connect*(-dc5.v_dd1#branch))

*dc2.vdd1 dc3.vdd1 dc4.vdd1 dc5.vdd1

.endc

.control

plot p1 p2 p3 p4 p5

.endc

.end

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Figure 8: Id vs Vdd (curve for power consumption with varying load) ========

CODE FOR OUT vs IN FOR VARYING LENGTH =========

*nmos char


*netlist

m1 out in 0 0 cmosn l=1u w=0.5u

* input output voltage sourcev_dd vdd 0 dc 3.3 v_in in 0 dc

3.3 pulse(0 3.3 0.1n 1n 1n 10u 20u) r0 vdd out 50

* analysis request

.dc v_in 0 3.3 0.4 .tran .01u

80u

*compute response for various widths

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.control foreach res 100 1k

100k alter r0 = $res run end

.endc

*iterations for various values

.control

foreach iter 1 2 3 setplot

dc$iter plot in out -

v_dd#branch

setplot tran$iter plot in out -

v_dd#branch end

.endc

.end

Figure 9: Id vs Vdd (curve for out vs in of invetor

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Figure 10: Id vs Vdd (curve for out vs in of inveter for varying resistance

Figure 11: Id vs Vdd (transient response of inverter for varying resistance

0.1.3 LAB 3: Study of MOS inverter with active load - NMOS and PMOS (pseudo)

Objective : For a MOS inverter with active load ,study the transfr functions ,noise margins ,effect on risetime and falltime, propogation delay ,power and energy consumed with length and width variations od pull up and pull down transistors.

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Figure 12: Id vs Vdd (Pseudo NMOS

Figure 13: Id vs Vdd (NMOS with load enhancement

============= CODE FOR ACTIVE LOAD ================


m1 dl dl out 0 cmosn l=.5u w=.5u m2 out in

0 0 cmosn l=.5u w=.5u

*sources m1 v_dd dl

0 dc 3.3 v_gg in 0 dc

3.3

.control

dc v_dd 0 3.3 .01 plot -

v_dd#branch vs 3.3-dl dc v_gg 0

3.3 .01 plot out vs in

.endc

.end

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Figure 14: Id vs Vdd (transient response and out vs in for pseudo NMOS

============== CODE FOR PSEUDO MOS ===============

*pseudo nmos char


*mos m1 out 0 vdd vdd cmosp l=1u w=0.2u

m2 out in 0 0 cmosn l=1u w=.5u

*sources

v_dd vdd 0 dc 3.3 v_in in 0

dc 3.3

.control foreach wd .1u

1u 5u alter m2 w= $wd

dc v_in 0 3.3 .01

run end plot dc1.out dc2.out

dc3.out

.endc

.end

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Figure 15: Input output graph for pseudo NMOS

Figure 16: pseudo transfer characheristics

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Figure 17: transfer characteristics pseudo MOS with varying load width

Figure 18: transfer characteristics for pseudo MOS with varing driver width

0.1.4 LAB 4: Study of CMOS Inverter

Objective : Study the transfer function, noise margin, effect on risetime ,falltime,propogation delay, power of CMOS inverter with variation in L and W of pullup and pulldown transistors.

=========== Code for varing length in CMOS inverter ===========

*pseudo nmos char


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*mos m1 out in vdd vdd cmosp l=1u w=1.5u


*sources


dc 3.3

.control foreach ld 1u 5u

10u alter m2 l= $ld dc

v_in 0 3.3 .01


dc3.out

.endc

.end

Figure 19: transfer characteristics of CMOS with varing driver length

=========== Code for varying width of CMOS inverter=============

*pseudo nmos char


*mos m1 out in vdd vdd cmosp l=1u w=1.5u


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*sources


dc 3.3

.control foreach wd .1u

1u 5u alter m2 w= $wd

dc v_in 0 3.3 .01


dc3.out

.endc

.end

Figure 20: transfer characteristics of CMOS with varing driver width

============ Code for cascading CMOS transistor =============

*cmos cascadination


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m1 o_1 in 0 0 cmosn l=1u w=.5u m2 o_2

o_1 0 0 cmosn l=1u w=.5u m3 out o_2 0

0 cmosn l=1u w=.5u

*define resistors r_1

vdd o_1 100k r_2 vdd

o_2 100k r_3 vdd out

100k

*define sources v_dd vdd 0 dc 3.3 v_in in 0 dc 3.3 pulse(0 3.3

0.1n 1n 1n 50n 100n) .control tran .001n 200n plot in o_1 plot

o_1 o_2 plot o_2 out

.endc

.end

Figure 21: transient analysis for cascaded CMOS transistors

0.1.5 LAB 5: Depletion MOS and I vs V characteristics of PMOS

Objective : study the behaviour of depletion MOS and PMOS transistors.

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============== CODE FOR DEPLETION MOS ===============

*include


*nmos m1 vdd out out 0 mynmos l=1u

w=.2u m2 out in 0 0 cmosn l=1u w=.2u

.model mynmos nmos level=1 vto=-0.7

*sources


dc 3.3

.control

dc v_in 0 3.3 0.01

run end plot out

plot deriv(out)

.endc

Figure 22: transient analysis and derivative for depletion MOS

============ Code for PMOS I vs V characteristics ============


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m1 drain in vdd -3.3 cmosp l=1u w=0.5u v_dd

vdd 0 dc -3.3 v_in in 0 dc -3.3 v_drain drain 0 dc

0

.control

dc v_in 0 -3.3 -.01 v_dd 0 -3.3 -1

run end plot -

v_dd#branch

.endc

Figure 23: I vs V characteristics for PMOS

0.1.6 LAB 6: study of CMOS gates

Objective : study the behaviour transfer function,noise margin, rise time ,fall time, propogation delay,paower of a CMOS gates like NAND ,NOR functions (2 input AND gate ,2 input OR gate) with variations in L and W of pullup and pulldown transistors.

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Figure 24: CMOS NAND gate

============== CODE FOR NAND GATE ================

*NAND Gate Implementation


M1 vdd1 A top1 0 cmosn L=1U W=10U

M2 top1 B 0 0 cmosn L=1U W=10U

M3 vdd1 A v_connect v_connect cmosp L=1U W=10U M4

vdd1 B v_connect v_connect cmosp L=1U W=10U

v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0 0

0 8NS 16NS) v_gs2 B 0 PULSE(0 3.3 0 0 0 16NS

32NS)

.control tran 0.1NS 32NS run end plot

tran1.A tran1.B tran1.vdd1

.endc

.end

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Figure 25: transient response for NAND gate for input a=0,b=0


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=============== CODE FOR AND GATE =================

top1 A v_connect v_connect cmosp L=1U W=10U *NAND Gate Implementation


M1 vdd1 A top1 0 cmosn L=1U W=10U

M2 top1 B 0 0 cmosn L=1U W=10U

M5 stage2 vdd1 0 cmosn L=1U W=10U

M3 vdd1 A v_connect v_connect cmosp L=1U W=10U

M4 vdd1 B v_connect v_connect cmosp L=1U W=10U M6 stage2

vdd1 v_connect v_connect cmosp L=1U W=10U



32NS)

.control tran 0.1NS 32NS run end plot tran1.A tran1.B

tran1.vdd1 tran1.stage2

.endc

.end

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Figure 28: transient response for AND gate for input a=0,b=0


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============== CODE FOR NOR GATE ================

*NOR Gate Implementation


M1 vdd1 A 0 0 cmosn L=1U W=10U

M2 vdd1 B 0 0 cmosn L=1U W=10U

M3 top1 A v_connect v_connect cmosp L=1U W=10U M4

vdd1 B top1 top1 cmosp L=1U W=10U



32NS)

.control tran 0.1NS 32NS run end plot

tran1.A tran1.B tran1.vdd1

.endc

.end

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Figure 31: CMOS OR gate

Figure 32: transient response for NOR gate for input a=1,b=0

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Figure 33: transient response for NOR gate for input a=1,b=1

================ CODE FOR OR GATE =================

*NOR Gate Implementation


M1 vdd1 A 0 0 cmosn L=2U W=4U

M2 vdd1 B 0 0 cmosn L=2U W=4U

M5 stage1 vdd1 0 0 cmosn L=2U W=4U

M3 top1 A v_connect v_connect cmosp L=2U W=12U

M4 vdd1 B top1 v_connect cmosp L=2U W=12U M6 stage1 vdd1

v_connect v_connect cmosp L=2U W=12U

v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0.1p 0.1p 0.1p

4NS 8NS) v_gs2 B 0 PULSE(0 3.3 0.1p 0.1p 0.1p 8NS 16NS)

.control foreach wid 12u 24u 36u

28u alter M3 W=$wid alter M4

W=$wid

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tran 0.1NS 20NS run

plot A B vdd1

end .endc

.end

Figure 34: transient response for OR gate for input a=0,b=0

Figure 35: transient response for OR gate for input a=0,b=1

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Figure 36: transient response for OR gate for all input combinations

0.2 MODULE-2 REPORT : LAYOUT DESIGNING WITH MAGIC

Number of experiments performed : 2

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0.2.1 Layout design for CMOS inverter

Figure 37: Layout design for CMOS inveter

Capacitances observed in the circuit :

C0 vss 0 2.8fF

C1 out 0 2.3fF

C2 vdd 0 2.8fF

C3 input 0 6.3fF