Version: 0.3
Page: 00
Application Note
4.3" COLOR AMOLED MODULE
MODEL NAME: H429ALN01 V0
For integrate with RM69032
< � >Preliminary Specification
< >Final Specification
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Record of Revision
Version Revise Date Page Content
0.0 AUG 26, 2013 First Draft
0.1 OCT 03,2013 Initial Code Update
0.2 NOV 27,2013 Initial code Update (Brightness control、Dimming function control) 0.3 DEC 13,2013
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MIPI Video timing parameter
Modify Power on sequence
Add E1 Register setting
Modify B0 Register setting
Modify BE Register setting
Brightness Control
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Contents A. Electrical Specifications..............................................................................................................................3
1. Main FPC Pin assignment—AMOLED Panel Input/Output Signal Interface ........................................3
B. AC Characteristics.......................................................................................................................................4
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A. Electrical Specifications
1. Main FPC Pin assignment—AMOLED Panel Input/Output Signal Interface
FPC_S Pin_name I/O Description
1 ELVDD Power AMOLED power positive
2 ELVDD Power AMOLED power positive
3 ELVSS Power AMOLED power Negative
4 ELVSS Power AMOLED power Negative
5 IOVDD Power Power supply for I/O
6 AVDD Power Power supply for analog
7 MTP I MTP(need to indicate to connect GND or NC)
8 XRES I Device reset signal
9 TE O Vsync(vertical sync)signal output from your panel to avoid
tearing effect
10 CTS0/ID0 - NC
11 CTS1/ID1 - NC
12 GND Power GND
13 GND Power GND
14 DSI_D0N I/O MDDI or MIPI data negative signal
15 DSI_D0P I/O MDDI or MIPI data positive signal
16 GND Power GND
17 DSI_CLKN I MDDI or MIPI strobe negative signal
18 DSI_CLKP I MDDI or MIPI strobe postive signal
19 GND Power GND
20 DSI_D1N I/O MDDI or MIPI data negative signal
21 DSI_D1P I/O MDDI or MIPI data positive signal
22 GND Power GND
23 SWIRE Power SWIRE signal for PWR IC to control OVSS voltage
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B. AC Characteristics (1) MIPI Interface Characteristics
HS Data Transmission Burst
HS clock transmission
Turnaround Procedure
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(2) MIPI Timing Parameters
Parameter Description MIN TYP MAX Unit Note
TCLK-POST
Time that the transmitter shall
continue sending HS clock after the
last associated Data Lane has
transitioned to LP mod
60 ns + 52*UI ns
TCLK-PRE
Time that the HS clock shall be
driven prior to any associated Data
Lane beginning the transition from
LP to HS mode
8 UI
TCLK-PREPARE Time to drive LP-00 to prepare for
HS clock transmission 38 95 ns
TCLK-TERM-EN
Time to enable Clock Lane receiver
line termination measured from when
Dn crosses VIL,MAX
38 ns
TCLK-TRAIL
Time to drive HS differential state
after last payload clock bit of a HS
transmission burst
60 ns
TCLK-PREPARE
+ TCLK-ZERO
TCLK-PREPARE + time for lead HS-
0 drive period before starting
Clock
300 ns
TD-TERM-EN
Time to enable Data Lane receiver
line termination measured from when
Dn crosses VIL,MAX.
35 ns
+ 4*UI ns
TEOT
Time from start of THS-TRAIL or TCLK-
TRAIL period to start of
LP-11 state
105 ns
+ 12*UI ns
THS-EXIT Time to drive LP-11 after HS burst 100 ns
THS-PREPARE Time to drive LP-00 to prepare for
HS transmission 40 ns + 4*UI
85 ns +
6*UI ns
THS-PREPARE +
THS-ZERO
THS-PREPARE + Time to drive HS-0
before the Sync sequence 145 ns + 10*UI ns
THS-SKIP Time-out at RX to ignore transition
period of EoT 40
55 ns +
4*UI ns
THS-TRAIL
Time to drive flipped differential state
after last payload data bit of a HS
transmission burst
max( 8*UI, 60
ns+ 4*UI ) ns
TTA-GET Time to drive LP-00 by new TX 5*TLPX ns
TTA-GO Time to drive LP-00 after Turnaround
Request 4*TLPX ns
TTA-SURETime-out before new TX side starts
driving TLPX 2*TLPX ns
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(3) VIDEO Parameters
Min typ Max Unit
Frame Frequency Cycle 58 60 62 Hz
Cycle 572 DCLK
HAdr 540 DCLK
HFP 14 DCLK
Hsync 4 DCLK
1 Line scanning
time
HBP 14 DCLK
Cycle 992 Line
VAdr 960 Line
VFP 14 Line
Vsync 4 Line
1 Frame scanning
time
VBP 14 Line
(4) REST Timing Characteristics
Reset input timing:
IOVCC=1.65 to 3.6V, VCI=2.5 to 3.6V, AGND=DGND=0V,
Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below.
RESX Pulse Action
Shorter than 5µs Reset Rejected
Longer than 15µs Reset
Between 5µs and 15µs Reset starts
(It depends on voltage and temperature condition.)
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Note 2. During the resetting period, the display will be blanked (The display is entering blanking
sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition for H/W reset.
Note 3. During Reset Complete Time, data in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX.
Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
Note 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command
cannot be sent for 120msec
.
(5) I/O Pin Status Characteristics
sleep in sleep out DSTB off
1 ELVDD 4.6V 4.6V GND GND
2 ELVDD 4.6V 4.6V GND
3 ELVSS -4.4V -4.4V GND GND
4 ELVSS -4.4V -4.4V GND GND
5 IOVDD 1.8V 1.8V 1.8V GND
6 VDD 2.85V 2.85V 2.85V GND
7 MTP HiZ HiZ HiZ HiZ
8 RESX I I I HiZ
9 TE O O O GND
10 ID0 I/O I/O I/O I/O
11 ID1 I/O I/O I/O I/O
12 AGND GND GND GND GND
13 AGND GND GND GND GND
14 DSI_D0N I/O I/O I/O HiZ
15 DSI_D0P I/O I/O I/O HiZ
16 AGND GND GND GND GND
17 DSI_CLKN I I I HiZ
18 DSI_CLKP I I I HiZ
19 AGND GND GND GND GND
20 DSI_D1N I I I HiZ
21 DSI_D1P I I I HiZ
22 AGND GND GND GND GND
23 OLED_EN O O O GND
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(6) Panel Scan direction
(7) I/O Power on/off Sequence
a. MIPI Power on/off sequence
IC Side RM69032
AMOLED Front View
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(8) Initial setting
Recommended Power on Initial Sequence
Address
Step Instruction/Parameters Delay
time R/W
MIPI
Data
Type MIPI Others
Data
hex. Description
1 Turn on VDD VDD=3.0V
2 Turn on VDDI VDDI=1.8V
3 Delay no limit
4 REST pin low 20us 6 REST pin high 7 Delay 5 ms
8 W F000 55
9 W F001 AA
10 W F002 52
11 W F003 08
12
W
0x39 F0
F004 00
13 W BD00 01
14 W BD01 5A
15 W BD02 14
16 W BD03 14
17
W
0x39 BD
BD04 00
18 W C800 80
19 W C801 12
20 W C802 00
21 W C803 00
22 W C804 01
23 W C805 00
24 W
0x39 C8
C806 0E
25 W C900 80
26 W C901 12
27 W C902 00
28 W C903 00
29 W C904 01
30 W C905 00
31 W
0x39 C9
C906 0E
32 W CA00 83
33 W CA01 D6
34 W CA02 00
35
W
0x39 CA
CA03 00
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36 W CA04 01
37 W CA05 00
38 W CA06 0E
39 W CB00 83
40 W CB01 D5
41 W CB02 00
42 W CB03 00
43 W CB04 01
44 W CB05 00
45
W
0x39 CB
CB06 0E
46 D100 80
47 D101 10
48
W 0x39 D1
D102 20
49 D200 80
50 D201 09
51
W 0X39 D2
D202 24
52 W 0x15 D0 D000 22
53 W F000 55
54 W F001 AA
55 W F002 52
56 W F003 08
57
W
0x39 F0
F004 02
58 W FE00 08
59
W 0x39 FE
FE01 50
60 W ED00 48
61 W ED01 00
62 W ED02 E0
63 W ED03 13
64 W ED04 08 W ED05 00
66 W
0x39 ED
ED06 0C
67 W C300 F2
68 W C301 95
69
W
0x39 C3
C302 04
70 W E900 00
71 W E901 36
72
W
0x39 E9
E902 0B
73 W 0x15 CA CA00 04
74 W E1 E100 00
75 W 0x39 F0 F000 55
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76 W F001 AA
77 W F002 52
78 W F003 08
79 W F004 01
80 W B000 00
81 W B001 00
82
W
0x39 B0
B002 00
83 W B400 07
84 W B401 07
85
W
0x39 B4
B402 07
86 W B500 07
87 W B501 07
88
W
0x39 B5
B502 07
89 W B600 44
90 W B601 44
91
W
0x39 B6
B602 44
92 W B900 04
93 W B901 04
94
W
0x39 B9
B902 04
95 W BA00 34
96 W BA01 34
97
W
0x39 BA
BA02 34
98 W BE00 22
99 W BE01 30
100 W
0x39 BE
BE02 70
101 W 0x15 35 3500 00
102 W 0x15 36 3600 02
103 W 0x15 C0 C000 20
104 W C200 17
105 W C201 17
106 W C202 17
107 W C203 17
108 W C204 17
109 W
0x39 C2
C205 15
110 Turn on peripheral packet 0x32
111 Sleep out W 0x05 11 1100 00
112 Delay 300 ms
113 Display on W 0x05 29 2900 00
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Recommended Power off Mode Sequence
Address
Step Instruction/Parameters Delay
time R/W
MIPI
Data
Type MIPI Others
Data
hex. Description
1 DIPOFF W 0x05 28 2800 00
2 SLPIN W 0x05 10 1000 00
3 delay 120ms
4 Power off
(9) Brightness
a. Brightness Control
1 W F000 55
2 W F001 AA
3 W F002 52
4 W F003 08
5
W
0x39 F0
F004 01
6 W CF CF00 XX
Note: Brightness setting is as follows:
Gray Level XX (HEX) Brightness Ratio
0 0 0
1 1 2/256
2 2 3/256
… … …
253 FD 254/256
254 FE 255/256
255 FF 1
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