Verilog in a Nutshell 1.3
Copyright © 2002 - 2009 by Doulos. All Rights Reserved 1
Verilog in a Nutshell
Verilog HDL in a nutshell provides a quick-reference to Verilog for VHDL users. It is
based on the Verilog-2001 standard.
Verilog Language Features
Verilog has C-like syntax and operators, except:
Operators ++, --, += etc and the serial operator “,” are not supported, and “=”
can’t be used in expressions.
Multiple statements must be enclosed by begin/end (series) or fork/join (parallel),
not {} as in C
Module ports may be mode input, inout or output and must be bits or bit vectors.
Bits are 4-valued (0, 1, X, Z)
There are 3 main data types: nets, variables and parameters.
Nets (wire, wireor, wireand, tri0, tri1, supply0, supply1, trireg) are used in
structural/gate level descriptions or as the target of continuous assignments (assign).
net types are “resolved” types: the type determines how bus conflicts and Z values
are treated.
Variables (reg – unsigned N-bit; integer – signed 32 bit, time – unsigned 64 bit,
real, realtime – signed 64 bit real) can only be assigned within procedures (i.e.
initial or always blocks)
output ports may be nets or variables. input and inout ports must be nets. Only nets
can be connected to an output or inout port in a module instance. Nets or variables
may be connected to input ports.
Verilog has a concept of the simulation cycle and delta times that is different from
VHDL. Ordering of events is deliberately random. Assignments to variables are
always instantaneous (like VHDL variables), unless the nonblocking assignment (<=)
is used. Several procedures can write to the same variable simultaneously. The last
one wins. There is no concept of bus resolution for variables.
2 Copyright © 2002 - 2009 by Doulos. All Rights Reserved
Procedural statements and control structures:
forever
statement
repeat (number)
statement
while (condition)
statement
for (assignment; condition; assignment)
statement
if (condition)
statement
else
statement
case (expression)
expression: statement
expression: statement
...
default: statement
endcase
begin : name
end
fork : name
join
disable name; // jumps out of named block – use to exit loops
variable = expression; // blocking procedural assignment
variable <= expression; // non-blocking procedural assignment
Cases need not be exclusive, exhaustive, or even constants! Unlike C no 'break' is
required.
There are two variants on the case statement: casez treats Z as an input don’t care,
casex treats both X and Z as don’t cares.
There is dedicated syntax for describing accurate timing information in technology
libraries (specify).
Verilog in a Nutshell 1.3
Copyright © 2002 - 2009 by Doulos. All Rights Reserved 3
Verilog versus VHDL Verilog has many similarities to VHDL; it should be relatively easy for a VHDL user to
pick up the basics of Verilog. The following table summarises some of the
correspondences.
Verilog VHDL
module NAME
#(parameter N)
(input A, B, output F);
...
endmodule
library IEEE;
use IEEE.Std_logic_1164.all;
entity NAME is
generic (N : integer);
port (A,B: in Std_logic;
F : out Std_logic);
end;
architecture ARCH of NAME is
begin
...
end;
localparam Width = 8; constant Width: Positive := 8;
wire W; signal W: Std_logic;
wire [3:0] V; signal V: Std_logic_vector(3 downto 0);
assign NET = Expression; SIG <= Expression; -- concurrent
MOD label (A, B); label: COMP port map (A, B);
MOD label (.P(A), .Q(B)); label: COMP port map (P => A, Q => B);
generate
genvar I;
for ( I=0; I<N; I=I+1) begin: G
// …;
end
endgenerate
G: for I in 0 to N-1 generate
--
end generate;
initial
begin
...
end
process
begin
...
wait;
end process;
always process
@(a or b) wait on a, b;
@(posedge clk) wait until Rising_edge(clk);
#10 wait for 10 ns;
wait (reset) if reset /= '1' then
wait until reset = '1';
end if;
4 Copyright © 2002 - 2009 by Doulos. All Rights Reserved
Verilog VHDL
& && and
| || or
~ ! not
^ xor
== =
!= /=
{A, B} A & B
32'bZ // fixed width (others => 'Z');
{N{1’bZ}} // N is constant (others => 'Z')
vector[index] vector(index)
vector[7:0] vector(7 downto 0)
1’B0 '0'
8’B01010101 "01010101"
case (expr)
0, 1, 2: F = 0;
default: F = 4’bx;
endcase
case expr is
when 0 | 1 | 2 => F <= "0000";
when others => F <= "----";
end case;
begin: LOOP
integer I;
for (I = 0; I < 8; I = I + 1)
begin
...
if (A[I] == 0) disable LOOP;
end
end
for I in 0 to 7 loop
...
exit when A(I) = '0';
end loop;
always @(posedge clk or posedge rst)
if (rst)
...
else
...
process (clk, rst)
begin
if rst = '1' then
...
elsif Rising_edge(clk) then
...
end if;
end process;
assign IO = En ? Data : 4’bZ; IO <= Data when En = '1' else "ZZZZ";
$display("Hello"); WRITE(L, String'("Hello"));
WRITELINE(OUTPUT, L);
task procedure
function function