UTBB-FDSOI Design &Migration Methodology
Philippe Flatresse
Technology R&D
Central CAD & Design Solutions
Outline
• Introduction
• Digital design in UTBB FD-SOI
• Standard Cells & Body biasing techniques
• SRAMs
• Analog design in UTBB FD-SOI
• Body bias generator
• ESD & IOs
• Circuit porting experience
• LDPC, MODAP examples
2
Sept 13
28nm Planar UTBB FD-SOI: Structure
Substrate
High-KMetal Gate
Ultra Thin Body & BOX Fully Depleted SOI transistor
Thin Body(7nm)
36 Masks:7ML
Dual Vt - Dual Oxide
3
Sept 13
28nm Planar UTBB FD-SOI: Advantages
Body-Bias
Hybrid zone
24nm
• Ultra thin body• Better SCE immunity
• Ultra thin BOX• Extended body biasing
• Total dielectric isolation• Latch up immunity
• No channel doping• Improved variability
• Easy Porting from Bulk
UTBB FD-SOI enables shorter channel length
4
Sept 13
28FDSOI Process Flow at a Glance 5
STI module
Wells i/iWells i/i
Hybrid block
Ch. SiGe
Wells i/iGate stack
FEOL modules
Spacers
Wells i/iRaised SD
Junctions
OP block
Wells i/iSilicide
Wells i/iContact
MEOL modules
M1 module
Wells i/iMx module
M2x module
MiM decap
Wells i/iM8x module
Wells i/iFar BEOL
BEOL modules
Same as bulkAdjustment vs bulkNew module
Not use in FDSOI
Caption:
Handle wafer
Thin box
RaisedSD
Rectangularcontact
MG
M1
STI
NiSi Vt Adjust
-7 masks over 28LP Bulk Technology
Devices Partitioning in 28nm UTBB FD-SOI
Device TypeUTBB
FD-SOIBULK
Logic 2Vt / PB0-16nm*
SRAM
Capacitance, Varactor
Drift MOS (OTP)
Digital I/O
Analog MOS
RF MOS
Resistors (Poly) (Active)
Diodes (antenna)
ESD Devices (FET)
(FET, diode, SCR)
Vertical Bipolar
UTBB FD-SOI
side
BoxSi
“HYBRID”Bulk side
(*) PB = Poly Bias28nm UTBB FD-SOI technology allows for modulating logic transistor effective gate length in the range 24-40nm for the authorized poly/contact pitch. The bias number (PB) indicates the additional value to the minimal length (24nm).
Key solutions for ESD protection & Performance enhancement
6
Sept 13
UTBB FD-SOI Design EcoSystem
• Planar UTBB FD-SOI uses a conventional (bulk) design flow
• Cadence, Mentor, Synopsys, • Apache, Atrenta
• 4-terminals spice models available, derived from PSP
• Major simulators supported
7
Sept 13
UTBB FD-SOI Specifics for power optimization
Adaptive VoltageScaling
Dynamic Voltage& Frequency
Scaling
Power / ClockGating
Process Monitoring &
Compensation
PowerSwitches
RTL Power Estimation
Reverse &Forward
Body Bias
Multi VtCapabilities
8
Sept 13
How to migrate Libraries on UTBB
• Full DP re-characterization with dedicated SOI models• Charac for various BB conditions depending on the performances targeted
• Retuning of limited number of critical IPs: Analog, IOs, Fuse
Analog IPsRedesign
9
Std-CellsPorting
MemoriesPorting
FusesRedesign
Power switchPorting
Analog IPRetuning
IO - ESD updateRetuning
Sept 13
Standard cells & Body bias techniques
Stdcell Offer11
Low Power: RVT/LVT 12T/8T
Mainstream: RVT/LVT 12T/8T
CORE
P0
P4
P10
P16
CLK(CLK, CORESYNC, CLKHP)
PR
ECO
CORI
CORR
SHIFT
SHIFT_EG
CORHP
PRHP
• High Density (8T) and High Performance (12T)
• Dual VT : RVT and LVT.
• Multi Channel Length (Poly Bias) cells ,
• Footprint compatible
Sept 13
Body Bias concept in UTBB FD-SOI
Vb
No area penalty compared to Bulk
Reuse of Bulk design techniques
Speed/Power control
12
Sept 13
Body Bias: Speed/Power control
Body Bias not degraded with scaling in FDSOIBody biasing fully inefficient in Finfet
13
Sept 13
Extended Body Bias Range in UTBB FD-SOI
BULK UTBB FD-SOI
IGIDL(RBB)
IPN(FBB)
NMOS PMOS
14
noBB
FBBRBB
-300mV +300mV
noBB
FBBRBB
-3V +3V
Efficient knob for speed/leakage optimization
Sept 13
-3V
UTBB FD-SOI: Extended Body Voltage Range• Conventional Well (CW) - RBB
p-Well n-Well
NMOS PMOSGndsn Vddsp
• Flip Well (FW) - FBB
n-Well p-Well
NMOS PMOSGndsn Gndsp
noBB
FBBRBB
+3V-3V
Vdd/2+ 300mV
noBB
FBBRBB
+3V
-300mV
Efficient knob for speed/leakage optimization
15
Sept 13
RBB/FBB Efficiency - Silicon Benchmark 16
Sept 13
UTBB FD-SOI: Constraints in RVT/LVT mixability
• RVT: Conventional Well (CW)
• LVT: Flip Well (FW)
p-Well n-Well
NMOS PMOSGndsn Vddsp
n-Well p-Well
NMOS PMOSGndsn Gndsp
Multi-Vt co-integration thanks to poly biasing
17
Sept 13
Extended Poly biasing in UTBB FD-SOI
From 24nm (PB0) up to 40nm (PB16)
• UTBB FD-SOI enables shorter channel length
• Enabling wider transistor effective gate length modulation
• CPP (Drawn) = 136 nm ( relaxed, min is 126nm)
Key solution for multi-VT & leakage optimization
18
Sept 13
Speed/leakage performances FDSOI versus Bulk19
• 28nm Bulk at 1.0v, WC, -40c
• 28nm FDSOI at 0.85v, WC, 125c
LVT- PB16
RVT- PB10
RVTPB0
LVT- PB10
LVT- PB4
LVT- PB0RVT- PB0
LVT- PB4
LVT- PB0
RVT- PB4
RVT- PB10
RVT- PB4
UTBB FD-SOI LVT [PB0-PB16] offers the same leakage range as RVT/LVT bulk flavors for better performances
GND
p-WELL
n-WELL
NMOSnetwork
PMOSnetwork
VDD
20
RVT LVT
Fine grain multi-VT co-integrationS3S 2013, Monterey - California
GND
n-WELL
p-WELL
NMOSnetwork
PMOSnetwork
GND
p-WELL
n-WELL
NMOSnetwork
PMOSnetwork
PB6
RVT-like SNW
GND
n-WELL
NMOSnetwork
PMOSnetwork
RVT
LVT
RVT-like and SNW solutions enable multi-VT like optimization
Sept 13
Single Well for Co-integration – “miX”-ing21
1,02; 398
1,33; 1814
1,52; 6363
1,43; 436
1,76; 1868
1,91; 4217
100
1000
10000
1,00 1,50 2,00
Leak
age
Pow
er @
FF
/125
C (m
W)
Frequency @ SS/WC_temp (GHz)
28LP @ 1.0V
28FD @ 1.0V
RVT
LVT
LVT
RVT/ RVTmix
LVTmix
SLVT
SLVT +26%
LVT +32%
RVT +40%
• Standard RVT/LVT mimicked thanks to• Forward body biasing, width sizing or poly biasing
• Single Well ease the remapping from Bulk to SOI• More than 30% higher performance for the same leakage as bulk
Sept 13
Porting methodology : Digital sections 22
RTL & PnR database (From Bulk)
Std. Flow with one type: • RTL Verif• Synthesis• Pnr• STA
• DRC + LVS + Extraction
RVT/LVT
mixed in Bulk?
• AFE Block
N Y
TOP Integration & Checks
• Replace Libs • STA• ECO
Post Layout Verif• PL Netlist + SDF + Sims
AMS Verification
Sept 13
28nm UTBB-FDSOI SRAM
28FDSOI SRAM Offer 24
Bit-cells 28LP 28FDSOI Comments
D120 cell
Gnds=0VVdds=Vdd
FBBmax=0.3VRBBmax=0.3V
RVT
Gnds=0VVdds=0V
Body biasFBBmax (V>0)=0.3VFull RBB (V<0)
B152 cell
Gnds=0VVdds=Vdd
FBBmax=0.3VRBBmax=0.3V
LVT(Flip-Well)
Gnds=0VVdds=0V
Body BiasFull FBB (V>0)RBBmax (V<0)=-0.3V
RF251 cell
6T-part: cf152LL/197LLRead-Port:
Gnds=0VVdds=Vdd
FBBmax=0.3VRBBmax=0.3V
RP(RVTLVT)
Gnds=0V
Full FBB (V>0)RBBmax (V<0)=-0.3V
L197 cell(ST specific)
Gnds=0VVdds=Vdd
FBBmax=0.3VRBBmax=0.3V
Single-WellGnds=0VVdds=0V
NMOS PMOS NMOS PMOS
NMOS PMOSNMOS PMOS
NMOS PMOS
NMOS NMOS
NMOS PMOS
Sept 13
SRAM Vmin Comparison 25
Sept 13
PPA with 28FDSOI at same voltage as 28Bulk
0
500
1000
1500
2000
0.5 2 8 32 128 512
Fre
qu
en
cy (
MH
z)
Capacity (Kbit)
C28LP_DPREGLV
C28LP_SPHDDR
C28LP_SPREGLVDR
C28SOI_DPREGLV
C28SOI_SPHDDR
C28SOI_SPREGLVDR
50
500
0.5 2 8 32 128 512
Lea
ka
ge
(u
W)
Capacity (Kbit)
C28LP_DPREGLV
C28LP_SPHDDR
C28LP_SPREGLVDR
C28SOI_DPREGLV
C28SOI_SPHDDR
C28SOI_SPREGLVDR
0
0.5
1
1.5
2
2.5
0.5 2 8 32 128 512
Acc
ess
Tim
e (
ns)
Capacity (Kbit)
C28LP_DPREGLV
C28LP_SPHDDR
C28LP_SPREGLVDR
C28SOI_DPREGLV
C28SOI_SPHDDR
C28SOI_SPREGLVDR
Access time reduction in FDSOI vs Bulk: DPREG : -44% / SPHD : -43% / SPREG : -36%
Max frequency gain in FDSOI vs BulkDPREG : 65% / SPHD : 77% / SPREG : 75%
Dynamic power saving in FDSOI vs Bulk DPREG : -13% / SPHD : -18% / SPREG : -14%
Leakage saving in FDSOI vs Bulk DPREG : -29% / SPHD : -19% / SPREG : -40%
0
5
10
15
20
25
0.5 2 8 32 128 512
Dy
na
mic
Po
we
r (
uW
/MH
z)
Capacity (Kbit)
C28LP_DPREGLV
C28LP_SPHDDR
C28LP_SPREGLVDR
C28SOI_DPREGLV
C28SOI_SPHDDR
C28SOI_SPREGLVDR
Timlng: Bulk and SOI@Slow 0.9V -40C leakage/Dynamic power : Bulk / FDSOI@Fast 1.0V 125C26
Sept 13
28nm UTBB-FDSOI Analog design
Porting methodology : Analog sections 28
Schematic (From Bulk): • RVT MOS : No Change• LVT MOS : Bulk connection change• CDM rules integration : Few changes in specific cases
Layout (From Bulk): • Pcell based : Automatic hybrid addition• Handcrafted : Manual Hybrid layer addition + Adjustment for spacing• CDM & Antenna rules integration : S/D need antenna check
Layout : • Clean DRC + LVS• Extract Post layout netlist
Characterization• Analog top simulations • Timing Extraction
TO Integration & Digital Flow
Post Layout Tuning• Schematic + Layout
• LVS, DRC, Extraction
~80% activity automated by PDK tools for Pcell based
designs
Sept 13
PLLs porting example: Analog blocks
• VCO (current controlled ring oscillator based design)• Using thin oxide transistors (SG) for high speed requirement (few GHz).
• Same current is kept in VCO to get same analog performances
• No power gain in this specific stage
• PFD (Phase Frequency Detector) and CP (Charge Pump) are compatible with direct porting with minor manual retuning
• Up to 60% leakage gain with UTBB EG (analog supply)
• ~10% dynamic power gain (analog supply)
• Bandgap: design retuning• Performances are intimately dependent on PNP characteristics
• A design update is needed here to restore identical performances in term of temperature control, PSRR, reference current spread and amplifier stability
29
Global PLL power status: 10-15% gain on dynamic and leakage powers
Sept 13
PLLs porting example: Digital blocks
• PLL is a mix of RVT and LVT blocks
• RVT blocks• UTBB FD-SOI RVT faster than bulk LP RVT
• Used in small blocks having overall low leakage contribution
• Blind and fast porting Layout unchanged
• ~10% gain on dynamic power, negligible PLL leakage v ariation
• LVT blocks• UTBB FD-SOI LVT much faster than bulk LP LVT but more leaking at constant definition
• 25% leakage gain by using speed/leakage tuning advantage of UTBB FD-SOI
• Higher PB => Same performance => Reduced leakage• No Area Penalty since the gate sizing is done at constant overall device size
• ~10% gain on dynamic power
30
UTBB PLL
Sept 13
Experience return for mixed signal IPs porting
• Low porting cycle time from 28nm LP to 28nm UTBB FD-SOI• ~3 months for complex IPs: LPDDR2 1066, PLLs up to 4.6Ghz, D-PHY 1Gbps
• …against ~twice effort when doing standard porting from Bulk to Bulk
• Leveraging on • Higher performances of UTBB devices• Layout compatibility with existing areas in Bulk• Automatic porting tools from PDK managing ~80% of activity to get DRC/LVS clean
• Porting from bulk using same design environment, at constant abstract• Secure concurrent development of whole SoC
• UTBB FD-SOI devices offering finer granularity in performance optimization• 2 Vt for thin and thick oxyde transistors
• Each Vt covering wider range of speed and leakage (LVT leakage tuning over 30x range)
• Power saving• Digital blocks of IPs: ~25% leakage power gain ; ~10% dynamic power gain
• Analog blocks of IPs: no generic value, depends on feature/performance specificity
31
Sept 13
Body-Bias Generator
Body-Bias voltages generation
• How to generate programmable body voltages ?
gnds grid
PW
PW
NM
OS
PM
OS
D-N
W
P-S
UBN
W
vdds grid
FBB : positive V 0V
t
FBB : negative V0Vt
DAC
0 → -1.3V
Neg. Charge Pump
1V8
GND
-1V8
DAC
0 → 1.3V
33
Sept 13
Output Amplifiers designgnds grid
1V8
GNDvdds grid
DAC
DAC Neg
Pump
-1V8
• AB-class for fast transients
• Symmetrical outputs
PW
PW
D-N
W
P-S
UB
NW
Vhigh
Vlow
• Low Vt PMOS
• Ultra-low Vt NMOS (full FBB)
Vhigh
Vlow
in+in- in-
+
+-
-
34
Sept 13
BBGEN ID card 35
Charge pump
Item Value
Size (µm) 400x800
Vbbp range 0 → -1300mV
Vbbn range 0 → 1300mV
Settling time0→|1300mV|
1.3µs @ max load
Quiescent current 4mA typ
Load range 1-20 nF + 10Ω min ESR
Techno Options None
BEOL 10ML
Supply 1.8V
Ext cap 1µF
Sept 13
ESD & IO Strategy in UTBB FD-SOI
Sept 13
Objectives
Slide 37
• Understand specific Fully-Depleted SOI (FDSOI)
technology constraints for the ESD designer
• Discuss ESD devices placement to reach the
optimum ESD performance
• Demonstrate the efficiency of Hybrid Bulk/FDSOI
co-integration to design ESD networks
37
Sept 13
ESD devices placement rules (1 of 4)
Slide 38
STI Diode
Not optimal due to high forward recovery time…
…but very high voltage tolerance
Shallow BOX kills the diode → Hybrid Bulk only
Gated Diode
Surface conduction makes it very efficient
Diode architecture also compatible with BOX
→ Hybrid Bulk OR Thin Film
38
Sept 13
ESD devices placement rules (2 of 4)
NFET operated as BigFET ESD Clamp
Operates in linear regime, no self-heating & BJT
→ Thin Film to benefit from better NFET perf. and body biasing features
MOS capacitance used for RC trigger circuit
Abrupt decrease in moderate inversion (FDSOI)
BOXVb Vt=f(Vb) ( 60-100mV/V)
39
Sept 13
ESD devices placement rules (3 of 4) Un-silicided ESD FETs used as lateral bipolars
GGNMOS Lateral bipolar conduction compatible with both Hybrid Bulk and Thin Film
but…
IO
Gnd
Vdd
Hybrid
Hybrid Thin Film
Layoutcompatibility
+ +
MaximumESD current
+ -
Triggeringvoltage
-(High)
+(Low)
FDSOI
40
Sept 13
ESD devices placement rules (4 of 4)How to protect thin film designs with Hybrid ESD dev ices ?
Innovative BIMOS concept in Hybrid Bulk
R
Cur
rent
[A]
Voltage [V]
R
Triggering voltage tuned by external resistance
Same High current performance than GGNMOS
41
Sept 13
0
0.5
1
1.5
2
0 2 4 6
Cur
rent
[A]
Voltage [V]
GGNMOS Hybrid
GGNMOS FDSOI
BIMOS Hybrid 10kOHMS
ESD FETs: Hybrid vs Thin Film• Silicon results: TLP(100ns) performance comparison
/2.8
42
Sept 13
Gated diodes: Hybrid vs Thin Film• Silicon results: (vf)TLP performance comparison
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 1.0 2.0 3.0 4.0
Cur
rent
[A]
Voltage [V]
HYBRID BULKFDSOI
9 ns
100 ns /2/2
43
Sept 13
ESD clamp SPICE comparison of different design scenarios.
R BOX
Design Scenario Leakage @Vdd
Vovershoot *(2kV HBM)
Vmax *(2kv HBM)
Reference = Bulk 28LP(clamp pwell@GND)
48nA 1.4V 1.5V
FDSOI/porting (Bulk direct porting)
4nA 1.4V 1.5V
FDSOI/boosted (dynamic body biasing) **
4nA 1.1V 1.3V
FDSOI/boosted_LVT(dynamic body biasing + ground
plane swap) **
40nA 0.9V 1.15V
**
Volta
ge
Time
*
23%
44
Standalone supply clamp analysis 40µm width IO power cell: ESD devices split
Hybrid
FDSOI
R
R
Secondary protection for non-calibrated ESD
RC triggered BigFET+ reverse diode
45
Sept 13
FDSOI/boosted_LVT design allows a 30% clamp width reduction wrt
28LP Bulk design
similar clamp placement rules with smaller clamp
Same clamp cell with relaxed placement rules
Application to the ESD remote network
30% gain
1mm(28LP Bulk) → 1.5mm(28nm FDSOI)
30% gain
46
FDSOI is latch-up free
• Remaining Injectors in Hybrid zones (mainly ESD devices). • LU between Hybrid parts.
• LU due to abutment between IO Pad and Wells (especially if NW@0V)
• Reduced set of LU rules apply on Hybrid zones
47
P+ N+ P+P+ N+ N+
Nwell
I/O PadVddeVss
P+
I/O Pad
VssNwE
Vdde
NwEI/O Core
Process induced damage in FDSOI
• In Bulk technology, Gatesare isolated from the substrate antenna rules to protect gates
• In SOI technology, both Gates and SD are isolated from the substrate antenna rules to protect gates and SD
N+
Pwell
Psub
P+
Nwell
N+
Pwell
Psub
P+
Nwell
V+ V+
V+ V+ V+ V+
48
Sept 13
ESD strategy 49
• ESD strategy is portable from Bulk to UTBB FD-SOI us ing Hybrid area
Advanced ESD Strategy
Distributed ESD clamps
Fully predictable by Spice simulations
Elementary devices UTBB silicon validated
Parameter Condition Minimum Value
ESD Voltage Protection
HBM 2kV
MM 100V
CDM 500V
Injection currentAmbient temperature 200mA
80°C 100mA
HBMMM
Sept 13
Bulk to UTBB-FDSOI:Circuit portability experience
UTBB FDSOI: Proof of concept
BULK LIKEDesign:
Conv. Well
UTBB FD-SOIDesign:Flip Well
Technologies28nm LP
FDSOI & BULK
Transistors150 Million
RVT, LVT, EG
Interconnect7 Cu Metal +
AL RDL
Die size 10mm²
LDPC core 0.25mm²
Vdd [0.35V; 1.5 V]
Vbb [-1V ; 1V]
51
Sept 13
0
100
200
300
400
500
600
0.3 0.5 0.7 0.9 1.1 1.3 1.5
Fre
qu
en
cy (
MH
z)
Vdd (V)
UTBB FD-SOI Max Frequency vs. BULK
Wide operating range 6MHz/0.35V to 525MHz/1.5V
BULK-LP (ref)
noBBFBB=1V
+73%
+168%
0.35V
+46%
FBB=0.3VUTBB FD-SOI
LDPC 6T-SRAM (FBB 1V) functional down to 0.41V
52
Sept 13
UTBB FD-SOI Total Power vs. BULK
0
2
4
6
8
No
rma
lize
d T
ota
l P
ow
er
(a.u
.)
Frequency (MHz)
0 100 200 300 400 500 600
noBB
FBB=1V
FBB=0.3V
BULK-LP
UTBB FD-SOI
Vdd: 0.6V to 1.5V step 100mV
Sept 13
28BULK - LP28UTBB - FW28UTBB - CW
UTBB FD-SOI Leakage Power vs. BULK
Wide body-bias modulation: 10X leakage benefit
0.01
0.1
1
10
Vback-bias (V)
RBB FBB
FWCW
UTBB range
Nor
mal
ized
Lea
kage
Pow
er(a
.u.)
-1 0 1Vdd=0.6VVdd=0.6V
10X
10X
2X
54
Sept 13
UTBB FD-SOI Energy Efficiency vs. BULK
50% EDP savings thanks to (Vdd, Vbb) modulation
0.4
0.6
0.8
1
1.2
1.4
0 2 4 6 8 10 12 14 16
En
erg
y D
ela
y P
rod
uct
(a
.u.)
Delay (ns)
0 2 4 6 8 10 12 14 16
BULK-LP
UTBB FD-SOI
(1V, 0.3V) => Ref(1V, 0.3V) => Ref
(0.8V, 0V) => -34%(0.8V, 0V) => -34%
(0.7V, 1V) => -50%(0.7V, 1V) => -50%
Vdd: 1.5V to 0.6V step 100mV
55
Sept 13
Half Node Effort for Full Node Benefit
RF7400RF7400
AB8540
DB8580
Dual qHD or WUXGADual qHD or WUXGA
12 Mpix & 5Mp12 Mpix & 5Mp
PMUPMU ChargingCharging AudioAudioUSB HSUSB HS SIMSIM
AV8100AV8100
ImagingISP
ImagingISP
GraphicsIMG SGX544-MP1
GraphicsIMG SGX544-MP1
PeripheralsPeripherals
RF7450RF7450 TranceiverTranceiverRF
front-endRF
front-end
SDMMCSD
MMC
eMMCeMMC eMMCeMMC
ARM® CortexARM® Cortex
A9A9 A9A9
NEONNEON
VideoVideo
HW Dec.HW Dec.
HW Enc.HW Enc. DisplayDisplay
CompositionComposition
NEONNEONLTE
HSPA+modem
LTEHSPA+modem
PoPPoP
LP-DDR533 MHzLP-DDR533 MHz
LP-DDR533 MHzLP-DDR533 MHz
CW1260CW1260
CG2905CG2905
ST21NFCAST21NFCA
e-SEe-SE
RF7400
AB8540
DB8580
Dual qHD or WUXGA
12 Mpix & 5Mp
PMU Charging AudioUSB HS SIM
AV8100
ImagingISP
GraphicsIMG SGX544-MP1
Peripherals
RF7450 TranceiverRF
front-end
SDMMC
eMMC eMMC
ARM® Cortex
A9 A9
NEON
Video
HW Dec.
HW Enc. Display
Composition
NEONLTE
HSPA+modem
PoP
LP-DDR533 MHz
LP-DDR533 MHz
CW1260
CG2905
ST21NFCA
e-SE
L8580
Great User Experience
• High performance system thanks to Dual 32bits LPDDR2 @ 533MHz support
• High quality 300dpi 4.5” HD display support
• Advanced 3D UI & Gaming with 1.2Gpx/s, 105Mtr/s & 22Gflops GPU
• Multi standard 1080p video codec's enabling Blue-Ray quality video
Mobile Broadband Everywhere
• 3GPP Rel. 8/9, LTE 100/50 Mbps, CA, HSPA+ 84/11 Mbps with MIMO and dual-cell capabilities
• TD-LTE/TD-SCDMA for Chinese market
• Worldwide coverage with up to 9 bands in one device
• Fully Leverage M7400 stand-alone LTE modem certification & deployment
Optimized Solution for Smartphones
• 28nm Single Chip LTE modem & Dual Core Application Processor @ 2.3GHz
• Best in class Low Power operation, 31DMIP/mW @ 0.6V
• Linux BSP for Android / Windows Phone 8
• Full set of connectivity
Combining Performance Boost with Best in Class Power Efficiency
28LP PG wk1229 FO wk124428FD PG wk1235 FO wk1243
Android booting wk1246CES show 2.8GHz + 0.63V/1GHz wk1302
28LP PG wk1229 FO wk124428FD PG wk1235 FO wk1243
Android booting wk1246CES show 2.8GHz + 0.63V/1GHz wk1302
56
UTBB FD-SOI SOC implementation experience
• Same design flow as for 28nm LP• Same tools used
• Same design cycle time
• For porting, used direct mapping of IPs + ECO• Script based
• Faster than rerunning synthesis
• Floorplan reuse
SOC in UTBB FD-SOI design effort is equivalentto a half node migration
57
Sept 13
UTBB FD-SOI key techniques for SOC implementation
Techniques Benefits
Full Flip Well implementation•Increased peak performance
•Increased energy efficiency
•Reduced leakage in idle mode
High performance L1Cache – 3GHz+
Multi OPP implementation
Aggressive body biasing
• CPU:
• Other SOC IPs
Techniques Benefits
Full RVT implementation •Fast execution
•Reduced dynamic power
•Reduced leakage in idle mode
Straightforward remapping from bulk
Reduced power supply
58
Sept 13
Dynamic Process Scaling (Body Bias) Advantage
Hit 3GHz Target
>80% extra speed @ 1.3V FBB1GHz with FD-SOI
28nm planar UTBB FD-SOI
Same Perfs as 28LP with 200mV Less-400mV with 1.3V FBB
59
Sept 13
Conclusion
• Breakthrough technology customers seeking a power/performance advantage
• UTBB librairies and Ips can be easily derived from Bulk
• Body Biasing techniques in UTBB-FDSOI• Key solution for high performance/low power application
• Best Speed / Power performances ever• Full Flexibility to cover full spectrum from LP to HP
• UTBB Credible alternative to FinFET
60
Sept 13
Acknowledgements
I would like to thank for their valuable support :
• CCDS & STD teams from STMicroelectronics
• CEA-LETI teams
61
Sept 13