USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB Type-C Active Cable ECNChristine Krause – Active Cable WG Chair
(Sponsored by Intel Corporation)
USB Developer Days 2017
Taipei, Taiwan
October 24 – 25, 2017
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Introduction
Scope Requirements for active cables
Organization ECN to USB Type-C Specification and Thermal Design Considerations
Outline Usage Models CC Requirements
Active Cable Definition SBU Requirements
USB PD Requirements USB 2.0
Response to USB PD Events USB 3.2
Power Requirements Return Loss
Thermal Requirements Alternate Modes
Shielding Effectiveness Thermal Design Considerations
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Potential Usage Models for <5m Active Cables• USB Type-C Full-Featured cable maximum reach
• USB 3.2 Gen1 ~2m• USB 3.2 Gen2 ~1m
• Use cases where USB Type-C Passive Full Feature Cables may not be long enough• Displays• Cameras• Machine Vision• Virtual Reality …
• Active Cables “just work”
• Future specification development for longer than 5m active cables as well as optically isolate cables is expected
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Active Cable Definition (5.2)• Active cables are designed to ‘just work’ like passive cables with no
discernable difference from the user’s perspective.
• Active cables minimally support USB 3.2 Gen 2x1.
• As multi-lane USB 3.2 and multi-lane USB 3.2 repeaters become common, all active cables will be required to support two lanes.
• Active cables support USB PD eMarkers and may support Alternate Modes and advertise them as defined in Section 5.2.6.
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Length USB PD VBUSVCONN
WiringCC USB 2.0 USB 3.2 SBU
< 5 m
SOP’ Required
(SOP’’ Optional)
3 A or 5 A
Same as passive cable
Same as passive cable
Same as passive cable
(Repeater)
Gen 2x1Gen 1x2Gen 2x2
Passive
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USB PD Requirements (5.2.1)• Support for eMarkers on SOP’ and optionally SOP”• Discover Identity
• Active Cable• SBU Supported• SBU Type• Maximum Operating Temperature• Shutdown Temperature• USB3 Gen1 U0 Latency• USB3 Gen2 U0 Latency• USB2 Support• USB3 Support, One or two lane support
• Cable Status• Internal Temperature of the plug• Thermal Shutdown indicator
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Response to USB PD Events (5.2.2.4)• Power Role Swap
• Maintain USB3.2 signaling during a Power Role Swap
• VCONN Swap• Maintain USB3.2 signaling during a Vconn Swap
• Fast Role Swap• Active cables will drop USB 3.2 signaling as a side-effect of a Fast Role Swap if
VCONN is not maintained during the Fast Role Swap
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Power Requirements (5.2.3 & 5.2.5.4.4)• VBUS
• All active cables meet the limits of the IR Drop on VBUS and ground defined in Section 4.4.1 (Same as passive cables)
• VCONN• Be capable of being powered from VCONN from only one port• Meet the VCONN sink requirement defined in Table 4-5 (to be updated) and Table 5-10.
Power dissipation targets are lower in active cables than passive cables because U3, Rx.Detect, or eSS.Disabled for extended periods with VCONN applied.
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State RequirementMaximum Power
ConsumptionVCONN
Target Power Consumption
VCONN
Power Consumption Notes
U0 Required1.0W 1-lane
1.5W 2-laneApplies to POLLING.LFPS, TRAINING, and RECOVERY states.
U1 Logically required ≤ U0 power Forwarding U1 LFPS is required
U2 Logically required ≤ U1 power Forwarding U2 LFPS is required
U3 Required 5 mW 2 mW eMarker in sleep.
Rx.Detect Required 5 mW 2 mWRx.Detect period may be lengthened when no USB 3.2 terminations have been detected. eMarker in sleep.
eSS.Disabled Required 5 mW 1 mW USB 3.2 is disabled. eMarker in sleep.
Table 5-10 USB 3.2 U-State Requirements Waivers to 10mW at introduction Goal power dissipation
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Mechanical Requirements• Same as Passive Cables
• Plug Spacing • Active cables support the USB Type-C vertical and horizontal spacing defined
Section 3.10.2 when functioning in USB 3.2 x1 operation
• However, this spacing may impose thermal constraints
• The Appendix D provides system design guidance to minimize the thermal impact due to connector spacing
• Products designed for USB 3.2 x2 operation with multiple adjacent USB Type-C connectors should follow Appendix D guidelines to minimize the likelihood the active cable will go into thermal shutdown
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Thermal Requirements (5.2.4.1.1)• Thermal Shutdown
• Place USB 3.2 signals in eSS.Disabled state when plug skin temperature reaches the maximum defined in Table 5-6
• Report thermal shutdown in USB PD Cable Status
• Maximum Skin Temperature• The active cable plug’s skin temperature should not exceed a maximum
operating temperature of 30 °C above the ambient temperature for a plastic/rubber housing and 15 °C for a metal housing in any operating mode
• Thermal shutdown occurs when the maximum plug skin temperature reaches the values defined in table 5-6 or lower
• Compliance will check the cable plug skin temperature with controlled motherboard and ambient temperatures
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Thermal Requirements (5.2.4.1.1)• Thermal Reporting
• Report maximum internal operating temperature in the USB PD Discover Identity Command
• Report current internal temperature in the USB PD Get Status Command.
• Report in °C and monotonic
• Cable manufacturers correlate the maximum internal operating temperature with the maximum plug skin temperature to ensure shutdown when the maximum plug skin temperature is reached
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Maximum Internal to Skin Temperature Offset Design specific
Maximum Internal Operating Temperature Design specific
Maximum Skin Temperature Plastic/Rubber1 80 °C
Maximum Skin Temperature Metal1 55 °C
Note 1: IEC 69950-1 reduced by 5 °C
Table 5-6 Cable Temperature Requirements
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Shielding Effectiveness (5.2.5.1)• Same as passive cables
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
CC Wire Requirements (5.2.5.2.1)• Same requirements as passive cables
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SBU Requirements (5.2.5.2.2)• Crosstalk same as passive cables (3.7.2.1)
• SBU Characteristics Active cable SBU end-to-end connections meet the requirements defined
in Table 5-7 when VCONN is present SBUs have no guaranteed performance when VCONN is not provided to the
cable The Host or Device should not provide any signal beyond what is defined
in Table 5-7
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Table 5-7 Active Cable SBU Characteristics
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Name Description Min Max Units
zCable_SBU Cable characteristic impedance on the SBU wires
32 53 Ω
tCableDelay_SBU Cable propagation delay on the SBU wire
26 ns
rCable_SBU DC resistance of SBU wires in the cable in USB
40 Ω
vCable_SBU Cable voltage swing on SBU wires
−0.3 4.0 V
Insertion Loss1 Cable insertion Loss 5 @ 0.5MHz
7 @ 1MHz
12 @ 10MHz
13 @ 25MHz
15 @ 50MHz
16 @ 100MHz
dB
iCableSBU Maximum end-to-end current -25 +25 mA
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 2.0 Requirements (5.2.5.3)• Same as passive cables
• Required to be passive
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 Architectures (5.2.5.4.1)• Active cables without at least one re-timer are out of scope.
• Active cables without re-timers connected to TP3 are out of scope.
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Host/device Host/device
RxTx
TxRx
Re-timer
Re-timer
Re-timer
Re-timer
TP2: Re-timer – TP3:Re-timer
Host/device Host/device
RxTx
TxRx
Re-timer
Re-timer
Re-driver
Re-driver
TP2: Re-driver – TP3:Re-timer
Host/device Host/device
RxTx
TxRx Re-timer
Re-timer
TP2: Passive – TP3:Re-timer
Host/device Host/device
RxTx
TxRx
Re-timer
Re-timer
Re-timer in center of cable
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 Power-on and Rx.Detect• Active cables perform far-end receiver termination detection per USB
3.2 Appendix E
• An active cable complete power-on and far-end receiver termination detection through the cable within tFWD_RX.DETECT
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Parameter Minimum Maximum Units
ZRX-HIGH-IMP-DC-POS per USB 3.2 per USB 3.2
RRX-DC per USB 3.2 per USB 3.2
tFWD-RX.DETECT 42 ms
Table 5-8 Active Cable Power-on Requirements
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 U0 Delay (5.2.5.4.4)
• Repeaters in active cables will meet the U0 delay requirements defined in USB 3.2 Appendix E
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USB 3.2 U-State Exit Latency (5.2.5.4.5)• Active cables will meet the U-state exit latency defined in USB 3.2
Appendix E
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 Signal Swing (5.2.5.4.6)• Test Points are defined the same was as in USB 3.2
• TP2 mid-point: defined to be after the mated receptacle/plug on the plug side with the plug test board with the traces de-embedded
• TP3 mid-point: defined to be after the mated receptacle/plug on the receptacle side with the USB Type-C cable test fixture
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Pkg
Ma
ted
Con
necto
r
TP1 TP2 TP3 TP4
Si
+
-
Txp
Txn
Ma
ted
Con
necto
r
Pkg
Si
+
-
Rxp
RxnActive Cable
Re
pe
ate
r
Re
pe
ate
r
Figure 5-8 SuperSpeed Electrical Test Points
Test Point
Description
TP1 Transmitter silicon padTP2 Transmitter port connector mid-pointTP3 Receiver port connector mid-pointTP4 Receiver silicon pad
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 Compliance Test Setup
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Figure 5-8 SuperSpeed Compliance Test Setup
Active Cable
Test
Fixture
Rx1p
Rx1n
Rx0n
Rx0p
Pattern
Generator
TP2
+-T
x1
p
T1
0n
TP4
Re
pe
ate
r
Re
pe
ate
r
Test
Fixture
Rx1p
Rx1n
Rx0n
Rx0p
TP1Pattern
Generator
+ -T
x0p
Tx0n
TP1 TP3Oscilloscope or
Error Detector
Tx
Aggressor
Tx
Aggressor
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 TP1 (5.2.5.4.6.1)• Normative (set at the pattern generator for compliance testing) – Subset of the USB 3.2 Spec
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Symbol Parameter Gen 1 (5.0 GT/s) Gen 2 (10 GT/s) Units Comments
VTX-DIFF-PP Differential p-p Tx voltage swing0.8 (min)
1.2 (max)
0.8 (min)
1.2 (max)V Nominal is 1 V p-p
VTX-DE-RATIO Tx de-emphasis USB 3.2 Table 6-17 −3.1+/-1.0 dBNominal is 3.5 dB for Gen 1 operation. Gen 2 transmitter equalization requirements are described in USB 3.2 Section 6.7.5.2.
VPRESHOOT Tx Preshoot USB 3.2 Table 6-17 2.2+/-1.0 dBGen 2 transmitter equalization requirements are described in USB 3.2 Section 6.7.5.2.
Table 5-11 Active Cable USB 3.2 Stressed Source Swing, TP1
Symbol Parameter Gen 1 (5GT/s) Gen 2 (10GT/s) Units Notes
f1 Tolerance corner 4.9 7.5 MHz
JRj Random Jitter 0.0121 0.0100 UI rms 1
JRj_p-p Random Jitter peak- peak at 10-12 0.17 0.14 UI p-p 1,4
JPj_500kHZ Sinusoidal Jitter 2 4.76 UI p-p 1,2,3
JPj_1Mhz Sinusoidal Jitter 1 2.03 UI p-p 1,2,3
JPj_2MHz Sinusoidal Jitter 0.5 0.87 UI p-p 1,2,3
JPj_4MHz Sinusoidal Jitter N/A 0.37 UI p-p 1,2,3
JPj_f1 Sinusoidal Jitter 0.2 0.17 UI p-p 1,2,3
JPj_50MHz Sinusoidal Jitter 0.2 0.17 UI p-p 1,2,3
JPj_100MHz Sinusoidal Jitter N/A 0.17 UI p-p 1,2,3
Table 5-12 Active Cable USB 3.2 Stressed Source Jitter, TP1 (Same as USB 3.2)
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 TP2 (5.2.5.4.6.2)
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• Informative (used to check the stressed signal for active cable JTOL testing)
• Design guidance for active cable input receiver
Symbol ParameterGen 1
(5.0 GT/s)Gen 2
(10 GT/s)Units Comments
VTX-DIFF-PP
Differential p-p Tx voltage swing
250 (min)
1000 (max )
250 (min )
850 (max )mV Nominal is 550mV p-p
VTX-DE-RATIO Tx de-emphasis0 (min)
4.0 (max)
2.1 (min)
4.1 (max)dB
There is no de-emphasis requirement for Gen1.
VPRESHOOT Tx Preshoot NA1.2 (min)
3.2 (max) dB
Applicable to USB3.2 Gen2 operation only
Table 5-13 Active Cable USB 3.2 Input Swing at TP2 (Informative)Tx1nTx1p
Rx0p
Tx0n
Rx0n
Tx0p
Rx1n
Rx1p
Full
Breakout
Pkg
TP1
Si
TP2
Tx1n
Tx1p
+-
+-
+-
+-
Rx0p
Tx0n
Rx0n
Tx0n
Rx1n
Rx1p
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 TP3 (5.2.5.4.6.3)• Informative (not used for compliance
testing)
• Design guidance for active cable output driver
• No De-emphasis required
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Symbol Parameter Gen 1 (5.0 GT/s)
Gen 2 (10 GT/s)
Units Comments
VRX-DIFF-PP-POST-EQ Differential Rx peak-to-peak voltage
300 (min)
850 (max)
300 (min )
850 (max )
mV Measured after the Rx EQ function (Section 6.8.2).
Nominal is 0.5 V p-p
VTX-DE-RATIO-GEN1 Tx de-emphasis0 (min)
4.0 (max)NA dB No preshoot allowed
VTX-DE-RATIO + VPRESHOOT-GEN2
Tx de-emphasis + Tx Preshoot
NA0 (min)
3.0 (max)dB
Sum of the de-emphasis and preshoot. There is no de-emphasis and pre-shoot requirement.
Table 5-14 Active Cable USB 3.2 Output Swing at TP3 (Informative)
CLB
Rx1p
Rx1n
Rx0n
Rx0p
HF-1C
Rx1n
Rx1p
Rx0p
Rx0n
Pkg
TP1
Si
TP2
Tx1n
Tx1p+-
+-
+-
Rx0p
Rx1n
Rx0n
Rx1p
Tx0n
Tx0p
TP3
+-
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB 3.2 TP4 (5.2.5.4.6.4)• Normative (tested in compliance)
• The active cable transmitter output is defined at TP4 for both high and low loss channels• The requirements for TP4 are defined in the USB3.2 specification Table 6-20• The input signal for the test will be applied at TP1 per Section 5.2.5.4.6.1
• The low loss test board will be used to test the maximum output swing• The maximum loss test board will be used to test the minimum output swing.
Jitter must be met with both test boards
• The active cable bit-error-rate will be tested at TP4 and meet or exceed a BER of 10-12• The error detector used will have the ability to remove SKP ordered sets
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB3.2 Test Points: TP4 (Rx Silicon Pad)
• Used for Tx eye measurement Eye height
TJ (using RJ measured @ TP3)
• In practice, signal is measured @ TP3 Compliance board is embedded by Sigtest.
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CLB
Rx1p
Rx1n
Rx0n
Rx0p
HF-1C
Rx1p
Rx1n
Rx0n
Rx0p
Pkg
TP1
Si
TP2
Tx1p
Tx1n
+-
+-
+-
+-
Rx1p
Rx1n
Rx0n
Rx1n
Tx0p
Tx0n
TP4
Active Cable
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Return Loss• Still under development
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Alternate Modes
• Discovery via USB PD• Discover SVIDs on SOP’ only
• Discover Modes on SOP’ only
• Enter/Exit Mode• Enter and Exit mode will be communicated on SOP’ and on SOP’’ when the SOP’’
Controller Present bit is set in the Active Cable• Recommend that Enter mode be sent initially to SOP’ and then SOP” if supported and then SOP
• Recommend Exit mode be sent initially to SOP and then to SOP” if supported and then SOP’
• Power In Alternate Mode• Maintain the plug’s Maximum Skin Temperature below the requirement defined in
Table 5-6
• Recommended to reduce power in sleep states
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Thermal Design Considerations (Appendix D)• Provides case studies to show the thermal impacts of certain factors
affecting the active cable maximum plug skin temperature• IC power
• VBUS Current
• Port Spacing
• Receptacle heat sinking
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Active Cable Model (Single Port, Top Mount Receptacle)
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Active Cable Thermal Design Considerations• Design the heat sink of cable to tradeoff flow to the cable plug and IC
temperature
• Design for maximum IC Junction temperature • This may be lower than the maximum plug skin temperature
• Design to shutdown at a cable plug skin temperature per Table 5-6 or lower• Cable vendors should build in margin to the specification
• Active cables may shutdown at lower temperatures that the specification allows
• Passive cables dissipate 250 mW in the plug at 5 A
• Active x1 cables dissipate 750 mW in the plug at 5 A (500 mW from electronics)
• Active x2 cables dissipate 1 W in the plug at 5 A (750 mW from electronics)
• This power has to be dissipated somehow
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USB3.2 x1 Single Port Spacing Simulations• Assumptions
• 500 mW power dissipation in each plug from electronics• 35 °C Ambient• 60 °C Thermal Boundary (motherboard temperature)• Plastic housing shell
• Requirements• TS (Plug skin temperature) must be less than 30 °C above ambient
• No special design considerations needed if motherboard is 60 °C maximum
• Thermal shutdown occurs by 80 °C TS (plug skin temperature)
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3 A VBUS 5 A VBUS
TS (°C) 57 60
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USB3.2 Multi-Port Spacing Considerations• Heat transfers between cables
• Heat dissipation through natural convection is less effective than in the single port case
• Radiation is less effective than in the single port case
• Center cable plug skin surface temperature is the hottest
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Vertically Stacked Horizontal Connectors 3x1 (VERT)
Horizontally Stacked Vertical Connectors 1x3 (HZ90)
Horizontally Stacked Horizontal Connectors 1x3 (HORZ)
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USB 3.2 x1 Multi-Port Spacing Simulations• Assumptions
• 35 °C Ambient, 60 °C Thermal Boundary (motherboard temperature)
• 500 mW power dissipation in each plug from electronics
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USB 3.2 x1 3A Active Cable in 3-port Configuration USB 3.2 x1 5A Active Cable in 3-port Configuration
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USB3.2 x1 Multi-Port Spacing Design Considerations
• 3 A Ports• It is possible to maintain the cable TS (plug skin temperature) at 30 °C above
ambient at minimum spacing with no special heat spreader or heat sink• The board thermal design should be simulated next to the receptacle and a
reasonable maximum temperature maintained
• 5 A Ports• It is not possible to maintain the cable TS at 30 °C above ambient at minimum
spacing in all orientations with no special heat spreader or heat sink in all cases
• Thermal simulation should be performed and minimum port spacing increased or a heat spreader or heat sink added to the board design
• The board thermal design should be simulated next to the receptacle and a reasonable maximum temperature maintained
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB3.2 x2 Single Port Spacing Simulations• Assumptions
• 750 mW power dissipation in each plug from electronics
• 35 °C Ambient
• 60 °C Thermal Boundary (motherboard temperature)
• Requirements• TS (Plug skin temperature) must be less than 30 °C above ambient
• No special design considerations needed if motherboard is 60 °C maximum
• Recommended that 5 A VBUS designs test and verify thermal designs
• Thermal shutdown occurs by 80 °C TS
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3A VBUS 5A VBUS
TS (°C) 61 64
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB3.2 x2 Multi-Port Spacing Results• Assumptions
• 35 °C Ambient, 60 °C Thermal Boundary (motherboard temperature)
• 750 mW power dissipation in each plug from electronics
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USB3.2 x2 3A Active Cable in 3-port Configuration USB3.2 x2 5A Active Cable in 3-port Configuration
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB3.2 x2 Multi-Port Spacing Design Considerations• 3 A Ports
• It is not possible to maintain the cable TS at 30 °C above ambient at minimum spacing with no special heat spreader or heat sink
• Thermal simulation should be performed and minimum port spacing increased or a heat spreader or heat sink added to the board design
• The board thermal design should be simulated next to the receptacle and a reasonable maximum temperature maintained
• 5 A Ports• It is not possible to maintain the cable TS at 30 °C above ambient at minimum
spacing with no special heat spreader or heat sink• Thermal simulation should be performed and minimum port spacing
increased AND a heat spreader or heat sink added to the board design• The board thermal design should be simulated next to the receptacle and a
reasonable maximum temperature maintained
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Summary of Design ConsiderationsRemember that Hosts, Hubs, and Devices do not control the type of cable connected or the ambient temperature
Designers must consider and simulate:
• Port Spacing and orientation
• USB Type-C Receptacle heat sink, spreader, or cooling
• Motherboard temperature
• VBUS Current per port
• Number of USB 3.2 lanes (x1 or x2)
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Q&A
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