8/16/2019 UPF Guide 2009
1/52
IEEE 1801
UPF Solutions Guide
July 200
8/16/2019 UPF Guide 2009
2/52
IEEE 1801-2009™ is an IEEE Standard for Design and Verification of
Low Power Circuits
The power supplied to elements in an electronic design affects the way circuits
operate. Although this is obvious when stated, today’s set of high-level design
languages have not had a consistent way to concisely represent the regions
of a design with different power provisions, nor the states of those regions or
domains. This standard provides an HDL-independent way of annotating a
design with power intent. In addition, the level-shifting and isolation between
power domains may be described for a specific implementation, from high-
level constraints to particular configurations. When the logic in a power domain
receives different power supply levels, the logic state of portions of the design
may be preserved with various state- retention strategies. This standard pro-
vides mechanisms for the refined and specific description of intent, effect, and
implementation of various retention strategies. Incorporating components into
designs is greatly assisted by the encapsulation and specification of the char-
acteristics of the power environment of the design and the power requirementsand capabilities of the components; this information encapsulation mechanism
is also described in this standard. The analysis of the various power modes of a
design is enabled with a combination of the description of the power modes and
the collection, generation, and propagation of switching information.
Order On-Line at: http://standards.ieee.org/prod-serv/index.html
Part Number: STD95919 Format: PDF ISBN: 978-0-7381-5929-4
UPF is a Copyright of Accellera. All other trademarks and copyrights belong
to their respective owners. There is no intent to violate anyone’s rights.
Latest UPF Solutions Guide can be downloaded from:
http://www.accellera.org/upf/SolutionsGuide.pdf
All the information contained in this solution guide about products and contacts
is provided by respective vendors. The user of this solution guide is requested
to check the latest product information by contacting the respective vendor.
This solution guide should not be used as the sole source of information for
making decisions regarding suitability of UPF or any UPF related products for
any purpose.
Original Version: July 2007
4th Edition: July 2009
For corrections and additions, please contact Yatin Trivedi, [email protected]
8/16/2019 UPF Guide 2009
3/52
July 2009 3
8/16/2019 UPF Guide 2009
4/52
4 July 2009
8/16/2019 UPF Guide 2009
5/52
July 2009 5
8/16/2019 UPF Guide 2009
6/52
6 July 2009
mailto:[email protected]
8/16/2019 UPF Guide 2009
7/52
July 2009 7
8/16/2019 UPF Guide 2009
8/52
8 July 2009
8/16/2019 UPF Guide 2009
9/52
July 2009 9
Low Power Design & Verification Flow
UPF
HDL(RTL)
UPF
Verilog(Netlist)
UPF
Verilog(Netlist)
Synthesis
P&R
S i m ul a t i on ,L o gi c al E q ui v a
l en c e C h e ck i n g ,…
8/16/2019 UPF Guide 2009
10/52
10 July 2009
8/16/2019 UPF Guide 2009
11/52
July 2009 11
8/16/2019 UPF Guide 2009
12/52
8/16/2019 UPF Guide 2009
13/52
8/16/2019 UPF Guide 2009
14/52
14 July 2009
mailto:[email protected]://www.atrenta.com/
8/16/2019 UPF Guide 2009
15/52
July 2009 15
MPSimSimulation
Testbench
RT
DesignerDebug
ProtometerCoverage
UPF Specification Simulate power off corruption Simulate retention and
save/restore of states
Simulate isolation and clamping
Trace complete power networkand switches
Visualize power switch states Visualize the states of powered
off blocks throughout simulation
Annotate powered off signals
Automate power verificationcombinations
Verify all possible powercombinations
Power verification closure
MPSim
Designer
ProtoMeter
8/16/2019 UPF Guide 2009
16/52
16 July 2009
mailto:[email protected]://www.axiom-da.com/
8/16/2019 UPF Guide 2009
17/52
July 2009 17
http://www.azuro.com/rubix/http://www.azuro.com/powercentric/
8/16/2019 UPF Guide 2009
18/52
18 July 2009
PowerCentric™ Clock TreeSynthesis
Rubix™ Clock ConcurrentOptimization
RTL
Synthesis
Initial Place
Routing
GDSII
CTS
Phys. Opt.
Post-CTS Opt.
Verilog
netlist
Placed
DEF
SDC
PowerCentric
PRO
Verilog
netlist
Placed
DEF
RTL
Synthesis
Initial Place
Routing
GDSII
CTS
Phys. Opt.
Post-CTS Opt.
Verilog
netlist
Placed
DEF
SDC
R ubix
PRO
Verilog
netlist
Placed
DEF
http://www.azuro.com/mailto:[email protected]://www.azuro.com/mailto:[email protected]:[email protected]://www.azuro.com/
8/16/2019 UPF Guide 2009
19/52
8/16/2019 UPF Guide 2009
20/52
20 July 2009
mailto:[email protected]://www.chipvision.com/
8/16/2019 UPF Guide 2009
21/52
July 2009 21
8/16/2019 UPF Guide 2009
22/52
22 July 2009
mailto:[email protected]://www.commonplatform.com/
8/16/2019 UPF Guide 2009
23/52
July 2009 23
➔Architecture exploration, use case profiling
➔Early Power and Temperature estimation
➔Automatic generation of UPF format
➔Package and cooling technique selection
IPPower Model Database
ACEplorer
Fast Electro-thermal Simulator
Platform model Use Case model
Electronic SystemSpecification
High Level Model Builder
Platform : Board, SoC, SiP, IP : Pow er intents, power related parameters,
architecture structu re, thermal behavior
Use cases
Activi ty
8/16/2019 UPF Guide 2009
24/52
24 July 2009
UPF
ACEplorer
Low power architecture capture :Power domains, voltage/clock network, power
reduction techniques modelling
System Structure Power Characterization
High Level Power Model
XML based
Standard RTL to GDSII flow
mailto:[email protected]:[email protected]://www.doceapower.com/
8/16/2019 UPF Guide 2009
25/52
July 2009 25
Specialty Blocks
SERDES and PLL
Memory CompilersHi-Performance and Low PowerFull Redundancy (Single & DualPort SRAM, 1, 2 & 4-Port RegFile
Custom Memory and
High Speed/High DensityStandard Cells >1GHZ Designs
Ultra High Density and Low Power
I/O Blocks
Standard Cells
Memories
Specialty High Speed I/O’s andStandard I/O cells
mailto:[email protected]://www.dolphin-ic.com/
8/16/2019 UPF Guide 2009
26/52
26 July 2009
mailto:[email protected]://www.elastix-corp.com/
8/16/2019 UPF Guide 2009
27/52
July 2009 27
http://www.ieee.org/web/standards/home/find.htmlhttp://standards.ieee.org/http://standards.ieee.org/corpforum/index.html
8/16/2019 UPF Guide 2009
28/52
28 July 2009
http://www.interrasystems.com/
8/16/2019 UPF Guide 2009
29/52
July 2009 29
mailto:[email protected]://www.interrasystems.com/
8/16/2019 UPF Guide 2009
30/52
8/16/2019 UPF Guide 2009
31/52
July 2009 31
mailto:[email protected]://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/
8/16/2019 UPF Guide 2009
32/52
32 July 2009
T
mailto:[email protected]://www.magma-da.com/
8/16/2019 UPF Guide 2009
33/52
July 2009 33
mailto:[email protected]://www.magma-da.com/
8/16/2019 UPF Guide 2009
34/52
34 July 2009
Vista Architect
Power-Aware TLM
Vista ArchitectVista Architect
Power Power -- Aware TLM Aware TLM
Catapult HLS Architectural
Trade-Off Analysis
Catapult HLSCatapult HLS Architectural Architectural
TradeTrade--Off AnalysisOff Analysis
RTL SynthesisRTL SynthesisRTL Synthesis
Olympus SoCMulti-Corner Multi-Mode
Place & Route
OlympusOlympus SoCSoCMulti Multi --Corner Multi Corner Multi --ModeMode
Place & RoutePlace & Route
Q u e s t a
Q u e s t a
F o r m
a l P r o
F F o r m
a l P r o
o r m
a l P r o
TestKompressTestKompressTestKompress
0-In ® CDC00--InIn ® CDCCDC
Calibre PERC CalibreCalibre PERC PERC
I E E E 1
8 0 1
( U P F )
I E E
E 1
8 0 1
( U P F )
I E E
E 1
8 0 1
( U P F )
Vista Architect
Power-Aware TLM
Vista ArchitectVista Architect
Power Power -- Aware TLM Aware TLM
Catapult HLS Architectural
Trade-Off Analysis
Catapult HLSCatapult HLS Architectural Architectural
TradeTrade--Off AnalysisOff Analysis
RTL SynthesisRTL SynthesisRTL Synthesis
Olympus SoCMulti-Corner Multi-Mode
Place & Route
OlympusOlympus SoCSoCMulti Multi --Corner Multi Corner Multi --ModeMode
Place & RoutePlace & Route
Q u e s t a
Q u e s t a
F o r m
a l P r o
F F o r m
a l P r o
o r m
a l P r o
TestKompressTestKompressTestKompress
0-In ® CDC00--InIn ® CDCCDC
Calibre PERC CalibreCalibre PERC PERC
I E E E 1
8 0 1
( U P F )
I E E
E 1
8 0 1
( U P F )
I E E
E 1
8 0 1
( U P F )
8/16/2019 UPF Guide 2009
35/52
July 2009 35
Synthesis
UPFUPF
HDL(RTL)
HDL(RTL)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
P&R
Q u e s t a
Q u e s t a
F o r m a l P r o
F F o r m a l P r o
o r m a l P r o
Synthesis
UPFUPF
HDL(RTL)
HDL(RTL)
UPFUPF
HDL(RTL)
HDL(RTL)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
UPFUPF
Verilog(Netlist)
Verilog(Netlist)
P&R
Q u e s t a
Q u e s t a
F o r m a l P r o
F F o r m a l P r o
o r m a l P r o
8/16/2019 UPF Guide 2009
36/52
8/16/2019 UPF Guide 2009
37/52
July 2009 37
http://www.mentor.com/products/ic_nanometer_design/cl_floorplan/olympus/index.cfmhttp://www.mentor.com/products/fvmailto:[email protected]://www.mentor.com/
8/16/2019 UPF Guide 2009
38/52
38 July 2009
mimasic Low Power SoC Design and Verification Services
mailto:[email protected]://www.mimasic.com/
8/16/2019 UPF Guide 2009
39/52
July 2009 39
8/16/2019 UPF Guide 2009
40/52
40 July 2009
mailto:[email protected]://www.sequencedesign.com/
8/16/2019 UPF Guide 2009
41/52
July 2009 41
mailto:[email protected]://www.springsoft.com/
8/16/2019 UPF Guide 2009
42/52
42 July 2009
Predictable Success
mailto:[email protected]://www.magma-da.com/http://www.synopsys.com/eclypse
8/16/2019 UPF Guide 2009
43/52
8/16/2019 UPF Guide 2009
44/52
44 July 2009
http://www.tsmc.com/
8/16/2019 UPF Guide 2009
45/52
July 2009 45
8/16/2019 UPF Guide 2009
46/52
46 July 2009
RTLcode
Floor Planning
IC Compiler
Netlist
Logic Synthesis & STA
PrimeTimeDesign Compiler
RTL Simulation
MVSIM
Floor plan
Place & RouteIC Compiler
Multi-Voltage Rule Checker
Power Analysis (PrimeRail)
Formal Checking (Formality)
Chip Finishing
RC Extraction (Star-RCXT)
DRC/LVS (Hercules)
UMC UPF Solu tions
• Standard Cell Libr aries • UPF tags/header embedd ed
• Timing & Power Models
• Techn ology Files
• Based on UMC ’ s premium
device models
• DRC / LVS / LPE inclu ded
• Reference Design Flow (*)
• EDA script examples
• Applicat ion notes
• Sil icon experimental docum ents
(*) Slated for availability in Q3 2008
http://www.umc.com/
8/16/2019 UPF Guide 2009
47/52
July 2009 47
8/16/2019 UPF Guide 2009
48/52
48 July 2009
mailto:[email protected]://www.viragelogic.com/
8/16/2019 UPF Guide 2009
49/52
July 2009 49
ISBN: 978-0-387-71818-7
mailto:[email protected]://www.lpmm-book.org/http://www.springer.com/
8/16/2019 UPF Guide 2009
50/52
50 July 2009
http://www.vmmcentral.org/cgi-bin/contactus.cgihttp://www.vmmcentral.org/vmmlp
8/16/2019 UPF Guide 2009
51/52
What is UPF?
Unified Power Format (UPF), a format to describe low power intent fordesign implementation, analysis and verification, is the standard developed by
Accellera as UPF 1.0 in February 2007 and ratified by IEEE as IEEE 1801™
Standard for Design and Verification of Low Power Circuits in March 2009.
It enables open, multi-vendor tool flows and solutions for low-power ASIC
and SoC design. The true value of a single, widely adopted standard is dem-
onstrated by interoperability of products from a range of EDA suppliers who
support the UPF standard. Designers of modern, low-power ICs are the ultimate
beneficiaries of UPF.
UPF 1.0 standard from Accellera is accessible to everyone. The latest version of
this document can be downloaded from Accellera’s website at:
http://www.accellera.org.
IEEE 1801 standard can be purchased from IEEE Standards website:http://standards.ieee.org/prod-serv/index.html
For more details on the IEEE 1801 Working Group activity, you can sign up for
1801 email group by sending an email to [email protected].
July 2009
8/16/2019 UPF Guide 2009
52/52
UPF Solutions Providers
Dolphin Technology